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CYWB0220ABS-BZXI PDF预览

CYWB0220ABS-BZXI

更新时间: 2024-11-05 20:37:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 外围集成电路
页数 文件大小 规格书
79页 824K
描述
Microprocessor Circuit, CMOS, PBGA121, 10 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-121

CYWB0220ABS-BZXI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TFBGA, BGA121,11X11,32Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.65
JESD-30 代码:S-PBGA-B121JESD-609代码:e1
长度:10 mm端子数量:121
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA121,11X11,32封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8,1.8/3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Controllers
最大供电电压:1.9 V最小供电电压:1.7 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:10 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

CYWB0220ABS-BZXI 数据手册

 浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第2页浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第3页浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第4页浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第5页浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第6页浏览型号CYWB0220ABS-BZXI的Datasheet PDF文件第7页 
CYWB022XX Family  
West Bridge®: Astoria™ USB and Mass  
Storage Peripheral Controller  
West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller  
Direct memory access (DMA) slave support  
Features  
FlexBoot  
Multimedia device support  
Up to two SD, SDIO, MMC, MMC+, and CE-ATA devices  
Processor can boot from the processor interface port  
Ultra low power, 1.8-V core operation  
Low power modes  
®
Supports Microsoft Media Transfer Protocol (MTP) with  
optimized data throughput  
Simultaneous Link to Independent Multimedia (SLIM®)  
architecture, enabling simultaneous and independent data  
paths between the processor and USB, and between the USB  
and mass storage  
Small footprint:  
3.91 × 3.91 × 0.55 mm 81-ball WLCSP (SP and Lite SP)  
6 × 6 × 1.0 mm 100-ball VFBGA  
11 × 11 × 1.4 mm 100-ball BGA  
10 × 10 × 1.20 mm 121-ball FBGA  
High-speed USB at 480 Mbps  
USB 2.0 compliant  
Supports I2C boot and processor boot  
Integrated USB switch  
Integrated USB 2.0 transceiver, smart serial interface engine  
16 programmable endpoints  
Selectable clock input frequencies  
19.2 MHz, 24 MHz, 26 MHz, and 48 MHz  
Applications  
GPIF (General Programmable Interface)  
Allows direct connection to most parallel interface  
Programmable waveform descriptors and configuration  
registers to define waveforms  
Supports multiple Ready (RDY) inputs and Control (CTL)  
outputs  
Cellular phones  
Portable media players  
Personal digital assistants  
Portable navigation devices  
Digital cameras  
Flexible processor interface that supports:  
Multiplexing and nonmultiplexing address and data interface  
SRAM interface  
POS terminals  
Pseudo cellular random access memory (CRAM) interface  
Portable video recorders  
Data cards and wireless dongles  
(Antioch interface)  
Pseudo NAND flash interface  
SPI (slave mode) interface  
Logic Block Diagram  
West BridgeTM AstoriaTM  
Control  
Registers  
uC  
Access Control  
P
U
SLIMTM  
SD/SDIO/  
MMC+/ CE- N-XpressTM  
ATA Block Engine  
Cypress  
Configurable Storage  
Interface  
S
Cypress Semiconductor Corporation  
Document Number: 001-13805 Rev. *L  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 1, 2012  

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