Datasheet > CYWB0125ABX-FDXI

CYWB0125ABX-FDXI

更新时间： 2024-11-18 09:46:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	362K
描述
West Bridge Antioch Memory-mapped interface to main processor

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中文翻译

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数据手册

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CYWB0125ABX-FDXI 数据手册

ADVANCE

INFORMATION

CYWB012X Family

West Bridge^®Antioch™

■ Selectable clock input frequencies

❐ 19.2 MHz, 24 MHz, 48 MHz

Features

■ SLIM^®architecture, allowing simultaneous and independent

data paths between processor and USB, and between USB

and mass storage

■ Expanded mass storage device support

❐ MMC/MMC+/SD

❐ CE-ATA for micro-HDD

❐ NAND Flash: × 8 or × 16, SLC

❐ Full NAND management (ECC, wear-leveling)

■ High speed USB at 480 Mbps

❐ USB 2.0 compliant

❐ Integrated USB2.0 transceiver, smart Serial Interface Engine

❐ 16 programmable endpoints

■ Expanded selectable clock input frequencies

❐ 19.2 MHz, 24 MHz, 26 MHz, 48 MHz

■ Mass storage device support

❐ MMC/MMC+/SD

❐ NAND Flash: × 8 or × 16, SLC

❐ Full NAND management (ECC, wear-leveling)

Applications

■ Cellular Phones

■ Portable Media Players

■ Personal Digital Assistants

■ Digital Cameras

■ Memory-mapped interface to main processor

■ DMA slave support

■ Ultra low power, 1.8 V core operation

■ Small footprint, 6 × 6 mm VFBGA and WLCSP

■ Portable Video Recorder

Logic Block Diagram

West Bridge Antioch

8051 MCU

Control Registers

Access Control

SLIM^TM

Mass Storage Interface

SD/MMC/CE-ATA

NAND

Cypress Semiconductor Corporation

Document #: 001-05898 Rev.*C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 14, 2011

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