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CYW2338LFI PDF预览

CYW2338LFI

更新时间： 2024-01-05 16:50:29
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 166K
描述
PLL Frequency Synthesizer, 4 X 4 MM, MLFP-20

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CYW2338LFI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DFN
包装说明：4 X 4 MM, MLFP-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8其他特性：SELECTABLE PRESCALER RATIOS OF 64/65 OR 128/129
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：S-XQCC-N20
JESD-609代码：e0长度：4 mm
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：VQCCN
封装等效代码：LCC20,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
座面最大高度：1 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

CYW2338LFI 数据手册

 浏览型号CYW2338LFI的Datasheet PDF文件第1页浏览型号CYW2338LFI的Datasheet PDF文件第3页浏览型号CYW2338LFI的Datasheet PDF文件第4页浏览型号CYW2338LFI的Datasheet PDF文件第5页浏览型号CYW2338LFI的Datasheet PDF文件第6页浏览型号CYW2338LFI的Datasheet PDF文件第7页 
PRELIMINARY  
CYW2338  
Pin Definitions  
Pin  
No.  
(TSSOP)  
Pin  
No.  
(CSP)  
Pin  
No.  
Pin  
Type  
Pin Name  
(MLF)  
Pin Description  
V
CC1  
1
2
3
24  
19  
20  
1
P
P
O
Power Supply Connection for PLL1 and PLL2: When pow-  
er is removed from both the VCC1 and VCC2 pins, all latched  
data is lost.  
VP1  
2
PLL1 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC  
of PLL1.  
DOPLL1  
3
PLL1 Charge Pump Output: The phase detector gain is  
IP/2π. Sense polarity can be reversed by setting the FC bit in  
software (via the Shift Register).  
FIN1  
5
6
5
6
3
4
I
I
Input to PLL1 Prescaler: Maximum frequency 2.5 GHz.  
FIN1#  
Complementary Input to PLL1 Prescaler: A bypass capac-  
itor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
OSC_IN  
8
8
6
I
Oscillator Input: This input has a VCC/2 threshold and CMOS  
logic level sensitivity.  
OSC_OUT  
FO/LD  
9
10  
11  
7
8
O
O
Oscillator Output  
10  
Lock Detect Pin of PLL1 Section: This output is HIGH when  
the loop is locked. It is multiplexed to the output of the pro-  
grammable counters or reference dividers in the test program  
mode. (Refer to Table 3 for configuration.)  
CLOCK  
11  
12  
9
I
Data Clock Input: One bit of data is loaded into the Shift  
Register on the rising edge of this signal.  
DATA  
LE  
12  
13  
14  
15  
10  
11  
I
I
Serial Data Input  
Load Enable: On the risingedge of this signal, thedatastored  
in the Shift Register is latched into the reference counter and  
configuration controls, PLL1 or PLL2 depending on the state  
of the control bits.  
FIN2#  
15  
17  
13  
I
Complementary Input to PLL2 Prescaler: A bypass capac-  
itor should be placed as close as possible to this pin and must  
be connected directly to the ground plane.  
FIN2  
16  
18  
18  
20  
14  
16  
I
Input to PLL2 Prescaler: Maximum frequency 1.1 GHz.  
DOPLL2  
O
PLL2 Charge Pump Output: The phase detector gain is  
IP/2π. Sense polarity can be reversed by setting the FC bit in  
software (via the Shift Register).  
VP2  
19  
20  
22  
23  
17  
18  
P
P
PLL2 Charge Pump Rail Voltage: This voltage accommo-  
dates VCO circuits with tuning voltages higher than the VCC  
of PLL2.  
VCC  
2
Power Supply Connections for PLL1 and PLL2: When  
power is removed from both the VCC1 and VCC2 pins, all  
latched data is lost.  
GND  
N/C  
4, 7, 14,  
17  
4,7,16, 2,5,12,  
G
Analog and Digital Ground Connections: This pin must be  
grounded.  
19  
15  
N/A  
1,9,13,  
21  
N/A  
N/C  
No Connect.  
2
1234567...12

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