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CYW2338BCITR PDF预览

CYW2338BCITR

更新时间: 2024-02-07 20:25:56
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 预分频器
页数 文件大小 规格书
12页 254K
描述
PLL Frequency Synthesizer, 3.50 X 4.50 MM, CSP-24

CYW2338BCITR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:TSSOP包装说明:0.173 INCH, TSSOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
其他特性:SELECTABLE PRESCALER RATIOS OF 64/65 OR 128/129模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm湿度敏感等级:1
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

CYW2338BCITR 数据手册

 浏览型号CYW2338BCITR的Datasheet PDF文件第3页浏览型号CYW2338BCITR的Datasheet PDF文件第4页浏览型号CYW2338BCITR的Datasheet PDF文件第5页浏览型号CYW2338BCITR的Datasheet PDF文件第7页浏览型号CYW2338BCITR的Datasheet PDF文件第8页浏览型号CYW2338BCITR的Datasheet PDF文件第9页 
PRELIMINARY  
CYW2338  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform[2, 3, 4, 5]  
//  
//  
//  
//  
PD = MSB  
PRE  
B1  
A7  
CNT2  
CNT1 = LSB  
DATA  
//  
//  
CLOCK  
t5  
t4  
t3  
t2  
t1  
//  
//  
//  
//  
LE  
t6  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1.  
Table 1. Control Configuration  
CNT1  
CNT2  
Function  
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector  
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.  
0
1
1
1
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector  
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1  
Program Counter for PLL2: A = 0 to 127, B = 3 to 2047, set PLL2 prescaler ratio, set  
PLL2 to power-down.  
Program Counter for PLL1: A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set  
PLL1 to power-down.  
Notes:  
2. t1–t6 = t > 50 ns  
3. CLOCK may remain HIGH after latching in data.  
4. DATA is shifted in with the MSB first.  
5. For DATA definitions, refer to Table 2.  
6

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