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CYM1831PZ-20C PDF预览

CYM1831PZ-20C

更新时间: 2024-11-04 22:10:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
8页 237K
描述
64K x 32 Static RAM Module

CYM1831PZ-20C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:ZIP包装说明:PLASTIC, ZIP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.87Is Samacsys:N
最长访问时间:20 ns其他特性:CONFIGURABLE AS 64K X 32
I/O 类型:COMMONJESD-30 代码:R-PZMA-T64
JESD-609代码:e0内存密度:2097152 bit
内存集成电路类型:SRAM MODULE内存宽度:32
功能数量:1端口数量:1
端子数量:64字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX32输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:ZIP封装等效代码:ZIP64/68,.1,.1
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:14.351 mm最大待机电流:0.16 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.96 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:1.27 mm
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

CYM1831PZ-20C 数据手册

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31  
CYM1831  
64K x 32 Static RAM Module  
on an epoxy laminate board with pins. Four chip selects (CS1,  
CS2, CS3, and CS4) are used to independently enable the four  
bytes. Reading or writing can be executed on individual bytes  
or any combination of multiple bytes through proper use of  
selects.  
Features  
High-density 2-Mbit SRAM module  
32-bit standard footprint supports densities from 16K  
x 32 through 1M x 32  
High-speed CMOS SRAMs  
Access time of 15 ns  
Low active power  
5.3W (max.)  
Writing to each byte is accomplished when the appropriate  
Chip Selects (CSN) and Write Enable (WE) inputs are both  
LOW. Data on the input/output pins (I/OX) is written into the  
memory location specified on the address pins (A0 through  
A15).  
SMD technology  
TTL-compatible inputs and outputs  
Low profile  
Reading the device is accomplished by taking the Chip Selects  
(CSN) LOW and Output Enable (OE) LOW while Write Enable  
(WE) remains HIGH. Under these conditions the contents of  
the memory location specified on the address pins will appear  
on the data input/output pins (I/OX).  
Max. height of 0.50 in.  
Small PCB footprint  
1.2 sq. in.  
The data input/output pins stay in the high-impedance state  
when Write Enable (WE) is LOW or the appropriate chip se-  
lects are HIGH.  
Functional Description  
Two pins (PD0 and PD1) are used to identify module memory  
density in applications where alternate versions of the  
JEDEC-standard modules can be interchanged.  
The CYM1831 is a high-performance 2-Mbit static RAM mod-  
ule organized as 64K words by 32 bits. This module is con-  
structed from eight 64K x 4 SRAMs in SOJ packages mounted  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
PD - OPEN  
0
GND  
1
I/O  
8
1
3
PD  
PD - GND  
2
4
6
0
1
PD  
I/O  
I/O  
I/O  
I/O  
V
A A  
0
1
2
3
0
15  
OE  
WE  
5
7
9
16  
I/O  
9
8
I/O  
I/O  
10  
11  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
CC  
A
0
A
A
7
1
64K x 4  
SRAM  
64K x 4  
I/O I/O  
I/O I/O  
7
A
8
0
3
4
A
2
SRAM  
4
4
4
4
4
4
4
4
A
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
CS  
1
GND  
64K x 4  
SRAM  
64K x 4  
SRAM  
I/O I/O  
I/O I/O  
WE  
8
11  
12  
15  
23  
31  
A
15  
A
14  
CS  
2
CS  
1
CS  
CS  
CS  
2
3
4
CS  
4
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
CS  
3
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
NC  
OE  
I/O  
NC  
64K x 4  
SRAM  
64K x 4  
SRAM  
I/O I/O  
I/O I/O  
16  
19  
20  
GND  
24  
I/O  
I/O  
I/O  
I/O  
A
A
A
16  
17  
I/O  
I/O  
I/O  
25  
26  
27  
18  
19  
10  
11  
12  
A
3
64K x 4  
SRAM  
64K x 4  
SRAM  
I/O I/O  
I/O I/O  
A
28  
24  
27  
4
5
A
V
CC  
A
13  
20  
21  
22  
23  
A
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
GND  
Cypress Semiconductor Corporation  
Document #: 38-05270 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised March 15, 2002  

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