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CYM1465A

更新时间： 2024-11-08 22:28:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
7页 168K
描述
512K x 8 PDIP Static RAM

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中文翻译

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CYM1465A 数据手册

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65A  
CYM1465A  
512K x 8 PDIP Static RAM  
an automatic power-down feature that reduces power con-  
sumption by more than 99% when deselected.  
Features  
• 4.5V–5.5V operation  
Writing to the SRAM is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
eight input/output pins (I/O0 through I/O7) of the device is then  
written into the memory location specified on the address pins  
(A0 through A18). Reading from the device is accomplished by  
taking chip select (CE) and output enable (OE) LOW while  
write enable (WE) remains inactive or HIGH. Under these con-  
ditions, the contents of the memory location specified on the  
address pins (A0 through A18) will appear on the eight appro-  
priate data input/output pins (I/O0 through I/O7).The eight in-  
put/output pins (I/O0 through I/O7) are placed in a high imped-  
ance state when the device is deselected (CE HIGH), the  
outputs are disabled (OE HIGH), or during a write operation  
(CE LOW, and WE LOW).  
• CMOS SRAM for optimum speed and power  
• Low active power (165 mW max.)  
• Low standby power (L Version)—(110 µW max)  
• 2V data retention (L Version)  
• JEDEC-compatible pinout  
• 32-pin, 0.6-inch-wide DIP package  
• TTL-compatible inputs and outputs  
Functional Description  
The CYM1465A is a high-performance CMOS static RAM or-  
ganized as 512K words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE), an active LOW  
Output Enable (OE), and three-state drivers. This device has  
The CYM1465A is available in a 32-pin 600-mil wide body  
PDIP package.  
Logic Block Diagram  
Pin Configuration  
DIP  
Top View  
1
2
3
4
32  
31  
30  
29  
A
18  
A
16  
A
14  
A
12  
V
CC  
S
A
15  
A
17  
WE  
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
7
13  
8
I/O  
0
A
INPUT BUFFER  
6
A
A
5
9
11  
0
I/O  
I/O  
1
A
A
1
4
A
4
A
OE  
3
2
A
5
6
A
10  
10  
11  
12  
13  
14  
15  
16  
A
2
A
A
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
1
A
512 x 256 x 8  
ARRAY  
7
12  
I/O  
3
I/O  
4
I/O  
5
A
A
0
7
A
14  
A
16  
A
17  
I/O  
I/O  
I/O  
0
1
2
6
5
4
3
GND  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Selection Guide  
CYM1465A-70  
CYM1465A-85  
Maximum Access Time (ns)  
70  
20  
20  
85  
20  
20  
Maximum Operating Current (mA)  
Maximum Standby Current (µA)  
Cypress Semiconductor Corporation  
Document #: 38-05269 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 15, 2002  
1234567

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