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CYM1465PD-100C PDF预览

CYM1465PD-100C

更新时间: 2024-02-25 14:36:14
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
6页 137K
描述
SRAM Module, 512KX8, 100ns, CMOS

CYM1465PD-100C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.29
Is Samacsys:N最长访问时间:100 ns
I/O 类型:COMMONJESD-30 代码:R-XDMA-T32
JESD-609代码:e0内存密度:4194304 bit
内存集成电路类型:SRAM MODULE内存宽度:8
功能数量:1端口数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8输出特性:3-STATE
可输出:YES封装主体材料:UNSPECIFIED
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.008 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.11 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

CYM1465PD-100C 数据手册

 浏览型号CYM1465PD-100C的Datasheet PDF文件第2页浏览型号CYM1465PD-100C的Datasheet PDF文件第3页浏览型号CYM1465PD-100C的Datasheet PDF文件第4页浏览型号CYM1465PD-100C的Datasheet PDF文件第5页浏览型号CYM1465PD-100C的Datasheet PDF文件第6页 
1CYM1465  
CYM1465  
512K x 8 SRAM Module  
Features  
Functional Description  
• High-density 4-megabit SRAM module  
• High-speed CMOS SRAMs  
— Access time of 70 ns  
• Low active power  
The CYM1465 is a high-performance 4-megabit static RAM  
module organized as 512K words by 8 bits. This module is  
constructed using four 128K x 8 RAMs mounted on a substrate  
with pins. A decoder is used to interpret the higher-order ad-  
dresses (A and A ) and to select one of the four RAMs.  
17  
18  
— 605 mW (max.)  
Writing to the module is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
eight input/output pins (I/O through I/O ) of the device is writ-  
• 2V data retention (L Version)  
• JEDEC-compatible pinout  
• 32-pin, 0.6-inch-wide DIP package  
• TTL-compatible inputs and outputs  
• Low profile  
0
7
ten into the memory location specified on the address pins (A  
0
through A ). Reading the device is accomplished by taking  
18  
chip select and output enable (OE) LOW while write enable  
remains inactive or HIGH. Under these conditions, the con-  
tents of the memory location specified on the address pins (A  
— Max. height of 0.27 in.  
• Small PCB footprint  
0
through A ) will appear on the eight appropriate data in-  
18  
put/output pins (I/O through I/O ).  
0
7
— 0.98 sq. in.  
The input/output pins remain in a high-impedance state unless  
the module is selected, outputs are enabled, and write enable  
is HIGH.  
Logic Block Diagram  
Pin Configuration  
DIP  
Top View  
A A  
0
16  
1
2
3
4
32  
31  
30  
29  
A
18  
A
16  
A
14  
A
12  
V
CC  
S
WE  
OE  
A
15  
A
17  
WE  
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
7
13  
128K x 8  
SRAM  
128K x 8  
SRAM  
A
A
6
8
A
A
A
5
9
11  
A
4
A
OE  
3
A
10  
10  
11  
12  
13  
14  
15  
16  
A
2
A
CS  
1
A
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
5
4
3
I/O  
I/O  
I/O  
0
1
2
A
A
17  
1 OF 4  
DECODER  
18  
128K x 8  
SRAM  
128K x 8  
SRAM  
GND  
CS  
1465–2  
I/O0 I/O7  
1465–1  
Selection Guide  
1465-70  
1465-85  
85  
1465-100  
100  
1465-120  
120  
1465-150  
150  
Maximum Access Time (ns)  
70  
110  
12  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
110  
110  
110  
110  
12  
12  
12  
12  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
January 1991 – Revised January 1995  

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