Datasheet > CYD36S72V18

CYD36S72V18

更新时间： 2024-11-08 01:08:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
53页	755K
描述
FullFlex Synchronous SDR Dual Port SRAM

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中文翻译

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数据手册

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CYD36S72V18 数据手册

CYDXXS72V18

CYDXXS36V18

CYDXXS18V18

FullFlex™ Synchronous SDR

Dual Port SRAM

FullFlex™ Synchronous SDR Dual Port SRAM

Features

Functional Description

■ True dual port memory enables simultaneous access the

shared array from each port

The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,

18-Mbit, and 36-Mbit synchronous, true dual port static RAMs

that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports

are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

■ Synchronous pipelined operation with single data rate (SDR)

operation on each port

❐ SDR interface at 200 MHz

❐ Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)

■ Selectable pipelined or flow-through mode

■ 1.5 V or 1.8 V core power supply

The advanced features include the following:

■ Commercial and Industrial temperature

■ IEEE 1149.1 JTAG boundary scan

■ Built in deterministic access control to manage address

collisions during simultaneous access to the same memory

location

■ Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36

and × 18) packages

■ Variable impedance matching (VIM) to improve data

transmission by matching the output driver impedance to the

line impedance

■ FullFlex72 family

❐ 36-Mbit: 512 K × 72 (CYD36S72V18)

❐ 18-Mbit: 256 K × 72 (CYD18S72V18)

❐ 9-Mbit: 128 K × 72 (CYD09S72V18)

■ Echo clocks to improve data transfer

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE₀or CE₁enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

■ FullFlex36 family

❐ 36-Mbit: 1 M × 36 (CYD36S36V18)

❐ 18-Mbit: 512 K × 36 (CYD18S36V18)

❐ 9-Mbit: 256 K × 36 (CYD09S36V18)

❐ 2-Mbit: 64 K × 36 (CYD02S36V18)

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

■ FullFlex18 family

❐ 36-Mbit: 2 M × 18 (CYD36S18V18)

❐ 18-Mbit: 1 M × 18 (CYD18S18V18)

❐ 9-Mbit: 512 K × 18 (CYD09S18V18)

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The Logic Block

Diagram on page 2 shows these features.

■ Built in deterministic access control to manage address

collisions

❐ Deterministic flag output upon collision detection

❐ Collision detection on back-to-back clock cycles

❐ First busy address readback

■ Advanced features for improved high speed data transfer and

flexibility

❐ Variable impedance matching (VIM)

❐ Echo clocks

❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),

1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port

❐ Burst counters for sequential memory access

❐ Mailbox with interrupt flags for message passing

❐ Dual chip enables for easy depth expansion

The FullFlex72 is offered in a 484-ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-ball fine pitch

BGA package except the 36-Mbit devices which are offered in

484-ball plastic BGA package.

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 5, 2013

12 3 4 5 6 7...53

中文翻译

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与CYD36S72V18相关器件

型号	品牌	获取价格	描述	数据表
CYD36S72V18-133BBI	CYPRESS	获取价格	Dual-Port SRAM, 512KX72, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLA
CYD36S72V18-133BGI	CYPRESS	获取价格	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLAS
CYD36S72V18-133BGXC	CYPRESS	获取价格	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD
CYD36S72V18-133BGXI	CYPRESS	获取价格	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD
CYD36S72V18-167BGXC	CYPRESS	获取价格	Dual-Port SRAM, 512KX72, 11ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD
CYD36S72V18-167BGXI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD36S72V18-167BGXI	ROCHESTER	获取价格	512KX72 DUAL-PORT SRAM, 4ns, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, P
CYD36S72V18-200BGXC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD36S72V18-200BGXC	ROCHESTER	获取价格	512KX72 DUAL-PORT SRAM, 3.3ns, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE,
CYDC064B08	CYPRESS	获取价格	1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

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