CY8C9520A
CY8C9540A
CY8C9560A
20-, 40-, and 60-Bit I/O Expander
with EEPROM
Features
Overview
■ I2C interface logic electrically compatible with SMBus
The CY8C95xxA is a multi-port I/O expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in I/O pins, number of PWMs,
and internal EEPROM size.
The CY8C95xxA operates as two I2C slave devices. The first
device is a multi port I/O expander (single I2C address to access
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
I/O data pins independently configurable as inputs, outputs,
Bi-directional input/outputs, or PWM outputs
■ 4/8/16 PWM sources with 8-bit resolution
■ Extendable soft addressing algorithm allowing flexible I2C
address configuration
■ Internal 3-/11-/27-Kbyte EEPROM
■ User default storage, I/O port settings in internal EEPROM
■ Optional EEPROM write disable (WD) input
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default
configuration is pulled up internally.
■ Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes
■ Internal power on reset (POR)
■ Internal configurable watchdog timer
The system master writes to the I/O configuration registers
through the I2C bus. Configuration and output register settings
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I2C
masters. The I2C slave in this device requires that the I2C master
supports clock stretching.
Top Level Block Diagram
WD
EEPROM
User
Settings
Area
User
Available
Area
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
Clocks
32 kHz
24 MHz
GPort 0
GPort 1
GPort 2
GPort 3
8 Bit IO
5 Bit IO
1.5 MHz
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
3 Bit IO
or A4-A6
93.75 kHz
4 Bit IO
or A1-A3, WD6
Divider (1-255)
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I2C data bus. The Extendable Soft
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
Control
Unit
PWM 0
8 Bit IO
8 Bit IO
PWM 15
GPort 7
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
SCL
SDA
INT
A0
Vdd
Vss
Power-on-Reset
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-12036 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 1, 2015
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