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CY8C9540A-24PVXI1 PDF预览

CY8C9540A-24PVXI1

更新时间： 2024-11-21 14:41:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
24页 738K
描述
Parallel I/O Port, CMOS, PDSO48, 0.300 INCH, LEAD FREE, SSOP-48

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CY8C9540A-24PVXI1 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：SSOP包装说明：,
针数：48Reach Compliance Code：compliant
风险等级：5.77Is Samacsys：N
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
湿度敏感等级：3端子数量：48
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified表面贴装：YES
技术：CMOS端子面层：Matte Tin (Sn)
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：30uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

CY8C9540A-24PVXI1 数据手册

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CY8C9520A, CY8C9540A  
CY8C9560A  
20-, 40-, and 60-Bit IO Expander with  
EEPROM  
Features  
Overview  
■ I2C™ interface logic electrically compatible with SMBus  
The CY8C95xxA is a multi-port IO expander with on board user  
available EEPROM and several PWM outputs. All devices in this  
family operate identically but differ in IO pins, number of PWMs,  
■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)  
IO data pins independently configurable as inputs, outputs,  
bi-directional input/outputs, or PWM outputs  
and internal EEPROM size.  
The CY8C95xxA operates as two I2C slave devices. The first  
device is a multi port IO expander (single I2C address to access  
all ports through registers). The second device is a serial  
EEPROM. Dedicated configuration registers can be used to  
disable the EEPROM. The EEPROM uses 2-byte addressing to  
support the 28 Kbyte EEPROM address space. The selected  
device is defined by the most significant bits of the I2C address  
or by specific register addressing.  
■ 4/8/16 PWM sources with 8-bit resolution  
■ Extendable Soft Addressing™ algorithm allowing flexible  
I2C-address configuration  
■ Internal 3-/11-/27-Kbyte EEPROM  
■ User default storage, IO port settings in internal EEPROM  
■ Optional EEPROM Write Disable (WD) input  
The IO expander's data pins can be independently assigned as  
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.  
The individual data pins can be configured as open drain or  
collector, strong drive (10 mA source, 25 mA sink), resistively  
pulled up or down, or high impedance. The factory default config-  
uration is pulled up internally.  
■ Interrupt output indicates input pin level changes and Pulse  
Width Modulator (PWM) state changes  
■ Internal Power On Reset (POR)  
■ Internal configurable Watchdog timer  
The system master writes to the IO configuration registers  
through the I2C bus. Configuration and output register settings  
are storable as user defaults in a dedicated section of the  
EEPROM. If user defaults were stored in EEPROM, they are  
restored to the ports at power up. While this device can share the  
bus with SMBus devices, it can only communicate with I2C  
masters.  
Top Level Block Diagram  
WD  
EEPROM  
User  
Settings  
Area  
User  
Available  
Area  
There is one dedicated pin that is configured as an interrupt  
output (INT) and can be connected to the interrupt logic of the  
system master. This signal can inform the system master that  
there is incoming data on its ports or that the PWM output state  
was changed.  
Clocks  
32 kHz  
24 MHz  
GPort 0  
GPort 1  
GPort 2  
GPort 3  
8 Bit IO  
5 Bit IO  
The EEPROM is byte readable and supports byte-by-byte  
writing. A pin can be configured as an EEPROM Write Disable  
(WD) input that blocks write operations when set high. The  
configuration registers can also disable EEPROM operations.  
1.5 MHz  
3 Bit IO  
or A4-A6  
93.75 kHz  
4 Bit IO  
or A1-A3, WD6  
The CY8C95xxA has one fixed address pin (A0) and up to six  
additional pins (A1-A6), which allow up to 128 devices to share  
a common two wire I2C data bus. The Extendable Soft  
Addressing algorithm provides the option to choose the number  
of pins needed to assign the desired address. Pins not used for  
address bits are available as GPIO pins.  
Divider (1-255)  
Control  
Unit  
PWM 0  
8 Bit IO  
8 Bit IO  
PWM 15  
GPort 7  
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)  
independently configurable 8-bit PWMs. These PWMs are listed  
as PWM0-PWM15. Each PWM can be clocked by one of six  
available clock sources.  
SCL  
SDA  
INT  
A0  
Vdd  
Vss  
Power-on-Reset  
For details on how to configure I2C, see Application Note  
"Communication - I2C Port Expander with Flash Storage -  
AN2304" at http://www.cypress.com/design/2304.  
Cypress Semiconductor Corporation  
Document Number: 38-12036 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 03, 2007  
[+] Feedback  
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与CY8C9540A-24PVXI1相关器件

型号 品牌 获取价格 描述 数据表
CY8C9540A-24PVXIT CYPRESS

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 		20-, 40-, and 60-Bit IO Expander with EEPROM
CY8C9540A-24PVXIT INFINEON

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 		CY8C95xx
CY8C9560 CYPRESS

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 		20-, 40-, and 60-Bit I/O Expander with EEPROM
CY8C9560-24AXI CYPRESS

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 		20-, 40-, and 60-Bit I/O Expander with EEPROM
CY8C9560-24AXIT CYPRESS

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 		20-, 40-, and 60-Bit I/O Expander with EEPROM
CY8C9560A CYPRESS

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 		20-, 40-, and 60-Bit IO Expander with EEPROM
CY8C9560A-24AXI CYPRESS

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 		20-, 40-, and 60-Bit IO Expander with EEPROM
CY8C9560A-24AXI INFINEON

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 		CY8C95xx
CY8C9560A-24AXI1 CYPRESS

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 		Parallel I/O Port, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY8C9560A-24AXIT CYPRESS

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 		20-, 40-, and 60-Bit IO Expander with EEPROM

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