Datasheet > CY8C9560A-24PVXI

CY8C9560A-24PVXI

更新时间： 2024-11-25 21:21:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		外围集成电路
页数	文件大小	规格书
32页	736K
描述
Parallel I/O Port, CMOS, PQFP100, LEAD FREE, TQFP-100

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技术参数
数据手册

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CY8C9560A-24PVXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	,
针数：	100	Reach Compliance Code：	compliant
风险等级：	5.76	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e3	湿度敏感等级：	3
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
表面贴装：	YES	技术：	CMOS
端子面层：	MATTE TIN	端子形式：	GULL WING
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

CY8C9560A-24PVXI 数据手册

CY8C9520A

CY8C9540A, CY8C9560A

20, 40, and 60 Bit I/O Expander with

EEPROM

Features

Overview

■ I²C interface logic electrically compatible with SMBus

The CY8C95xxA is a multi-port I/O expander with on board user

available EEPROM and several PWM outputs. All devices in this

family operate identically but differ in I/O pins, number of PWMs,

■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)

I/O data pins independently configurable as inputs, outputs,

Bi-directional input/outputs, or PWM outputs

and internal EEPROM size.

The CY8C95xxA operates as two I²C slave devices. The first

device is a multi port I/O expander (single I²C address to access

all ports through registers). The second device is a serial

EEPROM. Dedicated configuration registers can be used to

disable the EEPROM. The EEPROM uses 2-byte addressing to

support the 28 Kbyte EEPROM address space. The selected

device is defined by the most significant bits of the I²C address

or by specific register addressing.

■ 4/8/16 PWM sources with 8-bit resolution

■ Extendable soft addressing algorithm allowing flexible I²C

address configuration

■ Internal 3-/11-/27-Kbyte EEPROM

■ User default storage, I/O port settings in internal EEPROM

■ Optional EEPROM write disable (WD) input

The I/O expander's data pins can be independently assigned as

inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.

The individual data pins can be configured as open drain or

collector, strong drive (10 mA source, 25 mA sink), resistively

pulled up or down, or high impedance. The factory default config-

uration is pulled up internally.

■ Interrupt output indicates input pin level changes and pulse

width modulator (PWM) state changes

■ Internal power on reset (POR)

■ Internal configurable watchdog timer

The system master writes to the I/O configuration registers

through the I²C bus. Configuration and output register settings

are storable as user defaults in a dedicated section of the

EEPROM. If user defaults were stored in EEPROM, they are

restored to the ports at power up. While this device can share the

bus with SMBus devices, it can only communicate with I²C

masters. The I²C slave in this device requires that the I²C master

supports clock stretching.

Top Level Block Diagram

EEPROM

User

Settings

Area

User

Available

Area

There is one dedicated pin that is configured as an interrupt

output (INT) and can be connected to the interrupt logic of the

system master. This signal can inform the system master that

there is incoming data on its ports or that the PWM output state

was changed.

Clocks

32 kHz

24 MHz

GPort 0

GPort 1

GPort 2

GPort 3

8 Bit IO

5 Bit IO

1.5 MHz

The EEPROM is byte readable and supports byte-by-byte

writing. A pin can be configured as an EEPROM Write Disable

(WD) input that blocks write operations when set high. The

configuration registers can also disable EEPROM operations.

3 Bit IO

or A4-A6

93.75 kHz

4 Bit IO

or A1-A3, WD6

Divider (1-255)

The CY8C95xxA has one fixed address pin (A0) and up to six

additional pins (A1-A6), which allow up to 128 devices to share

a common two wire I²C data bus. The Extendable Soft

Addressing algorithm provides the option to choose the number

of pins needed to assign the desired address. Pins not used for

address bits are available as GPIO pins.

Control

Unit

PWM 0

8 Bit IO

PWM 15

GPort 7

There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)

independently configurable 8-bit PWMs. These PWMs are listed

as PWM0-PWM15. Each PWM can be clocked by one of six

available clock sources.

For details on how to configure I²C, see Application Note

"Communication - I²C Port Expander with Flash Storage -

AN2304" at http://www.cypress.com.

SCL

SDA

INT

V_dd

V_ss

Power-on-Reset

Cypress Semiconductor Corporation

Document Number: 38-12036 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised December 14, 2010

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