Datasheet > CY8C5668LTI-LP014

CY8C5668LTI-LP014

更新时间： 2024-02-17 06:04:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
120页	3755K
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Programmable System-on-Chip (PSoCÂ®)

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CY8C5668LTI-LP014 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFN	包装说明：	HVQCCN, LCC68,.32SQ,16
针数：	68	Reach Compliance Code：	compliant
ECCN代码：	3A991.A.3	HTS代码：	8542.31.00.01
Factory Lead Time：	1 week	风险等级：	5.67
边界扫描：	YES	总线兼容性：	I2C; USB; PS/2
最大时钟频率：	33 MHz	JESD-30 代码：	S-XQCC-N68
JESD-609代码：	e4	长度：	8 mm
湿度敏感等级：	3	I/O 线路数量：	48
端子数量：	68	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC68,.32SQ,16
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	RAM（字数）：	32768
ROM大小（位）：	2097152 Bits	座面最大高度：	1 mm
子类别：	Other uPs/uCs/Peripheral ICs	最大供电电压：	5.5 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD	端子节距：	0.4 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
紫外线可擦：	N	宽度：	8 mm
Base Number Matches：	1

CY8C5668LTI-LP014 数据手册

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PSoC^®5LP: CY8C56LP Family

Datasheet

very low power internal low-speed oscillator (ILO) for the sleep

and watchdog timers. A 32.768-kHz external watch crystal is

also supported for use in RTC applications. The clocks, together

with programmable clock dividers, provide the flexibility to

integrate most timing requirements.

2. Pinouts

Each VDDIO pin powers a specific set of I/O pins. (The USBIOs

are powered from VDDD.) Using the VDDIO pins, a single PSoC

can support multiple voltage levels, reducing the need for

off-chip level shifters. The black lines drawn on the pinout

diagrams in Figure 2-3 and Figure 2-4 show the pins that are

The CY8C56LP family supports a wide supply operating range

from 1.71 to 5.5 V. This allows operation from regulated supplies

such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or

directly from a wide range of battery types. In addition, it provides

an integrated high efficiency synchronous boost converter that

can power the device from supply voltages as low as 0.5 V. This

enables the device to be powered directly from a single battery.

In addition, you can use the boost converter to generate other

voltages required by the device, such as a 3.3 V supply for LCD

glass drive. The boost’s output is available on the VBOOST pin,

allowing other devices in the application to be powered from the

PSoC.

Each VDDIO may source up to 100 mA total to its associated I/O

pins, as shown in Figure 2-1.

Figure 2-1. VDDIO Current Limit

I_{DDIO X}= 100 mA

V_{DDIO X}

I/O Pins

PSoC supports a wide range of low power modes. These include

a 300 nA hibernate mode with RAM retention and a 2 µA sleep

mode with RTC. In the second mode the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

PSoC

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 3.1 mA when the CPU is running at

6 MHz.

The details of the PSoC power modes are covered in the “Power

System” section on page 24 of this datasheet.

Conversely, for the 100-pin and 68-pin devices, the set of I/O

pins associated with any VDDIO may sink up to 100 mA total, as

shown in Figure 2-2.

PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for

programming, debug, and test. Using these standard interfaces

you can debug or program the PSoC with a variety of hardware

solutions from Cypress or third party vendors. The Cortex-M3

debug and trace modules include Flash Patch and Breakpoint

(FPB), Data Watchpoint and Trace (DWT), Embedded Trace

Macrocell (ETM), and Instrumentation Trace Macrocell (ITM).

These modules have many features to help solve difficult debug

and trace problems. Details of the programming, test, and

debugging interfaces are discussed in the “Programming, Debug

Interfaces, Resources” section on page 57 of this datasheet.

Figure 2-2. I/O Pins Current Limit

Ipins = 100 mA

V_{DDIO X}

I/O Pins

PSoC

V_SSD

Note

4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84935 Rev. *C

Page 5 of 120

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CY8C5668LTI-LP014 替代型号

型号	品牌	替代类型	描述	数据表
CY8C5468LTI-037	CYPRESS	类似代替	Programmable System-on-Chip (PSoC?)
CY8C5467LTI-007	CYPRESS	类似代替	Programmable System-on-Chip (PSoC?)

与CY8C5668LTI-LP014相关器件

型号	品牌	获取价格	描述	数据表
CY8C5688AXI-LP099	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, TQFP-100
CY8C5688AXI-LP099	INFINEON	获取价格	CY8C56LPxxx
CY8C5688FNI-LP211	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PBGA99, WLCSP-99
CY8C5688LTI-LP086	CYPRESS	获取价格	Multifunction Peripheral, CMOS, QFN-68
CY8C5688LTI-LP086	INFINEON	获取价格	CY8C56LPxxx
CY8C56LP	CYPRESS	获取价格	Programmable System-on-Chip (PSoCÂ®)
CY8C56LP_13	CYPRESS	获取价格	Programmable System-on-Chip (PSoCÂ®)
CY8C5866AXI-LP020	CYPRESS	获取价格	Programmable System-on-Chip (PSoCÂ®)
CY8C5866AXI-LP020	INFINEON	获取价格	CY8C58LPxxx
CY8C5866AXI-LP021	CYPRESS	获取价格	Programmable System-on-Chip (PSoCÂ®)

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