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CY8C5688FNI-LP211 PDF预览

CY8C5688FNI-LP211

更新时间: 2024-02-23 11:46:41
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
125页 5673K
描述
Multifunction Peripheral, CMOS, PBGA99, WLCSP-99

CY8C5688FNI-LP211 技术参数

生命周期:Active包装说明:WLCSP-99
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.75边界扫描:YES
总线兼容性:I2C; USB最大时钟频率:33 MHz
JESD-30 代码:R-PBGA-B99长度:5.94 mm
I/O 线路数量:62端子数量:99
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
RAM(字数):32768座面最大高度:0.6 mm
最大供电电压:5.5 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM宽度:5.192 mm
Base Number Matches:1

CY8C5688FNI-LP211 数据手册

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PSoC® 5LP: CY8C56LP Family  
Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and  
a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:  
„ 32-bit ARM Cortex-M3 core plus DMA controller and digital filter processor, at up to 80 MHz  
„ Ultra low power with industry's widest voltage range  
„ Programmable digital and analog peripherals enable custom functions  
„ Flexible routing of any analog or digital peripheral function to any pin  
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable  
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and  
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.  
Features  
„ Operating characteristics  
„ Analog peripherals  
‡ Voltage range: 1.71 to 5.5 V, up to 6 power domains  
‡ Configurable 8- to 12-bit delta-sigma ADC  
‡ Up to two 12-bit SAR ADCs  
‡ Four 8-bit DACs  
‡ Temperature range (ambient) –40 to 85 °C[1]  
‡ DC to 80-MHz operation  
‡ Four comparators  
‡ Power modes  
• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz  
• 2-µA sleep mode  
• 300-nA hibernate mode with RAM retention  
‡ Four opamps  
‡ Four programmable analog blocks, to create:  
• Programmable gain amplifier (PGA)  
• Transimpedance amplifier (TIA)  
• Mixer  
• Sample and hold circuit  
‡ CapSense® support, up to 62 sensors  
‡ 1.024 V ±0.1% internal voltage reference  
‡ Boost regulator from 0.5-V input up to 5-V output  
„ Performance  
‡ 32-bit ARM Cortex-M3 CPU, 32 interrupt inputs  
‡ 24-channel direct memory access (DMA) controller  
‡ 24-bit 64-tap fixed-point digital filter processor (DFB)  
„ Versatile I/O system  
„ Memories  
‡ 48 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)  
‡ Up to eight performance I/O (SIO) pins  
• 25 mA current sink  
‡ Up to 256 KB program flash, with cache and security features  
‡ Up to 32 KB additional flash for error correcting code (ECC)  
‡ Up to 64 KB RAM  
• Programmable input threshold and output high voltages  
• Can act as a general-purpose comparator  
• Hot swap capability and overvoltage tolerance  
‡ Two USBIO pins that can be used as GPIOs  
‡ Route any digital or analog peripheral to any GPIO  
‡ LCD direct drive from any GPIO, up to 46 × 16 segments  
‡ CapSense support from any GPIO  
‡ 2 KB EEPROM  
„ Digital peripherals  
‡ Four 16-bit timer, counter, and PWM (TCPWM) blocks  
‡ I2C, 1 Mbps bus speed  
‡ USB 2.0 certified Full-Speed (FS) 12 Mbps  
‡ Full CAN 2.0b, 16 Rx, 8 Tx buffers  
‡ 20 to 24 universal digital blocks (UDB), programmable to  
create any number of functions:  
‡ 1.2-V to 5.5-V interface voltages, up to four power domains  
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs  
„ Programming, debug, and trace  
• I2C, UART, SPI, I2S, LIN 2.0 interfaces  
• Cyclic redundancy check (CRC)  
• Pseudo random sequence (PRS) generators  
• Quadrature decoders  
‡ JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire  
viewer (SWV), and Traceport (5-wire) interfaces  
‡ ARM debug and trace modules embedded in the CPU core  
‡ Bootloader programming through I2C, SPI, UART, USB, and  
other interfaces  
• Gate-level logic functions  
„ Package options: 68-pin QFN and 100-pin TQFP  
„ Programmable clocking  
„ Development support with free PSoC Creator™ tool  
‡ Schematic and firmware design support  
‡ 3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz  
‡ 4- to 25-MHz external crystal oscillator  
‡ Internal PLL clock generation up to 80 MHz  
‡ Low-power internal oscillator at 1, 33, and 100 kHz  
‡ 32.768-kHz external watch crystal oscillator  
‡ 12 clock dividers routable to any peripheral or I/O  
‡ Over 100 PSoC Components™ integrate multiple ICs and  
system interfaces into one PSoC. Components are free  
embedded ICs represented by icons. Drag and drop  
component icons to design systems in PSoC Creator.  
‡ Includes free GCC compiler, supports Keil/ARM MDK  
compiler  
‡ Supports device programming and debugging  
Note  
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Document Number: 001-84935 Rev. *F  
Revised May 22, 2014  

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