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CY8C5668LTI-LP014 PDF预览

CY8C5668LTI-LP014

更新时间: 2024-02-13 23:10:40
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
120页 3755K
描述
Programmable System-on-Chip (PSoC®)

CY8C5668LTI-LP014 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC68,.32SQ,16
针数:68Reach Compliance Code:compliant
ECCN代码:3A991.A.3HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.67
边界扫描:YES总线兼容性:I2C; USB; PS/2
最大时钟频率:33 MHzJESD-30 代码:S-XQCC-N68
JESD-609代码:e4长度:8 mm
湿度敏感等级:3I/O 线路数量:48
端子数量:68最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC68,.32SQ,16
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2/5 V
认证状态:Not QualifiedRAM(字数):32768
ROM大小(位):2097152 Bits座面最大高度:1 mm
子类别:Other uPs/uCs/Peripheral ICs最大供电电压:5.5 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
紫外线可擦:N宽度:8 mm
Base Number Matches:1

CY8C5668LTI-LP014 数据手册

 浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第3页浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第4页浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第5页浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第7页浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第8页浏览型号CY8C5668LTI-LP014的Datasheet PDF文件第9页 
PSoC® 5LP: CY8C56LP Family  
Datasheet  
Figure 2-3. 68-pin QFN Part Pinout[5]  
(TRACEDATA[2], GPIO) P2[6]  
(TRACEDATA[3], GPIO) P2[7]  
(I2C0: SCL, SIO) P12[4]  
P0[3] (GPIO, OPAMP0-/EXTREF0)  
P0[2] (GPIO, OPAMP0+/SAR1 EXTREF)  
P0[1] (GPIO, OPAMP0OUT)  
1
2
3
4
5
6
51  
50  
49  
48  
47  
Lines show VDDIO  
to I/O supply  
association  
(I2C0: SDA, SIO) P12[5]  
P0[0] (GPIO, OPAMP2OUT)  
VSSB  
IND  
P12[3] (SIO)  
P12[2] (SIO)  
VSSD  
VDDA  
VSSA  
46  
45  
VBOOST  
VBAT  
7
8
9
44  
43  
42  
41  
QFN  
(TOP VIEW)  
VSSD  
VCCA  
10  
XRES  
(TMS, SWDIO, GPIO) P1[0]  
(TCK, SWDCK, GPIO) P1[1]  
(Configurable XRES, GPIO) P1[2]  
P15[3] (GPIO, KHZ XTAL: XI)  
P15[2] (GPIO, KHZ XTAL: XO)  
11  
12  
13  
40  
39  
P12[1] (SIO, I2C1: SDA)  
P12[0] (SIO, 12C1: SCL)  
(TDO, SWV, GPIO) P1[3] 14  
38  
37  
36  
35  
(TDI, GPIO) P1[4]  
(NTRST, GPIO) P1[5]  
VDDIO1  
15  
16  
17  
P3[7] (GPIO, OPAMP3OUT)  
P3[6] (GPIO, OPAMP1OUT)  
VDDIO3  
Notes  
5. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to  
ground, it should be electrically floated and not connected to any other signal.  
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.  
Document Number: 001-84935 Rev. *C  
Page 6 of 120  

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