PSoC® 5LP: CY8C58LP Family
Datasheet
PRELIMINARY
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C58LP family is also a high-performance configurable digital system with
some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN).
In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and
a high-performance 32-bit ARM® Cortex™-M3 microprocessor core. You can easily create system-level designs using a rich library
of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP
family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute
design changes through simple firmware updates.
❐ Library of advanced peripherals
Features
■ 32-bit ARM Cortex-M3 CPU core
❐ DC to 67 MHz operation
❐ 2F0la-syheaprroregtreanmtiomne, manodrym, uupltitpole25s6ecKuBri,ty10fe0a,0tu0r0eswrite cycles,
❐ tUiopntosto32ra-KgeB flash error correcting code (ECC) or configura-
❐ Up to 64 KB SRAM
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
■ Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
❐ +1.8052°4CV ±0.1% internal voltage reference across –40°C to
❐ Configurable delta-sigma ADC with 8- to 20-bit resolution
• Sample rates up to 192 ksps
❐ (2E-KEBPRelOecMtr)icmaellymeorrays, a1bMlecpyrocglersa,mamndab2l0e yreeaadrs-orneltyemnteiomnory
❐ A24H-Bch[1a]nbnuesl adcirceecstsmemory access (DMA) with multilayer
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
ratio (SINAD), ±1-bit INL/DNL
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
■ Low voltage, ultra low power
❐ Wide operating voltage range: 0.5 V to 5.5 V
❐ 5H.i0ghV-eofufictpieuntcy boost regulator from 0.5 V input to 1.8 V to
❐ Up to two SAR ADCs, each 12-bit at 1 Msps
❐ Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs
❐ Four comparators with 95-ns response time
❐ Four uncommitted opamps with 25-mA drive capability
❐ 3.1 mA at 6 MHz
❐ Low power modes including:
❐ fFigouurractoionnfsigaurreabpleromgrualmtifumnacbtiloengaaninalaomg pbllioficekrs(.PEGxAam), ptrlaenc-on-
simpedance amplifier (TIA), mixer, and sample and hold
• 2-µA sleep mode with real time clock (RTC) and low-volt-
age detect (LVD) interrupt
❐ CapSense support
• 300-nA hibernate mode with RAM retention
■ Programming, debug, and trace
■ Versatile I/O system
❐ vJiTeAwGer(4(SwWirVe)),,saenrdiaTl wRiAreCdEePbOuRgT(SinWteDr)fa(c2ewsire), single wire
❐ Cortex-M3 flash patch and breakpoint (FPB) block
❐ 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs[2]
)
❐ Any GPIO to any digital or analog peripheral routability
❐ LCD direct drive from any GPIO, up to 46×16 segments
❐ CapSense® support from any GPIO[3]
❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains
❐ Maskable, independent IRQ on any pin or port
❐ Schmitt-trigger transistor-transistor logic (TTL) inputs
❐ pAullllG-uPpI/Opusllc-odnofwignu,rHabigleh-aZs, oorpestnrodnrgainouhtpiguht/low,
❐ Configurable GPIO pin state at power-on reset (POR)
❐ 25 mA sink on SIO
❐ aCtoersteaxn-Min3stErumcbtioenddtreadceTrsatcreeaMma.crocell™ (ETM™) gener-
❐ tCraocrteexin-Mfo3rmdaattiaonwatchpoint and trace (DWT) generates data
❐ uCsoerdtefxo-rMp3riInntsf-tsrutymleednetabtuiogngiTnrgace Macrocell (ITM) can be
❐ aDnWdTt,raEcTeMs,yasntedmITsMvbialotchkesScWomVmournTicRaAteCwEiPthOoRffT-chipdebug
❐ Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
■ Digital peripherals
■ Precision, programmable clocking
❐ d2i0gittoal2b4lopcrkosgr(aUmDmBsa)ble logic device (PLD) based universal
❐ a3g- teor6a2n-gMeHz internal oscillator over full temperature and volt-
❐ 4- to 25-MHz crystal oscillator for crystal PPM accuracy
❐ Internal PLL clock generation up to 67 MHz
❐ Full CAN 2.0b 16 RX, 8 TX buffers[2]
❐ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
❐ Four 16-bit configurable timers, counters, and PWM blocks
❐ 32.768-kHz watch crystal oscillator
❐ Low power internal oscillator at 1, 33, and 100 kHz
❐ i6m7p-MleHmze,n2t4fi-nbiittefiixmepduplsoeinrtedspigoitnaslefil(tFeIrRb)loacnkd(iDnfFinBit)etoimpulse
■ Temperature and packaging
❐ –40 °C to +85 °C degrees industrial temperature
❐ 68-pin QFN and 100-pin TQFP package options.
response (IIR) filters
❐ Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 115 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-84932 Rev. **
Revised December 7, 2012
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