Datasheet > CY8C5488AXI-LP120

CY8C5488AXI-LP120

更新时间： 2024-11-11 19:42:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
126页	4536K
描述
Multifunction Peripheral, CMOS, PQFP100, TQFP-100

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CY8C5488AXI-LP120 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TQFP-100	Reach Compliance Code：	compliant
ECCN代码：	3A991.A.3	HTS代码：	8542.31.00.01
Factory Lead Time：	1 week	风险等级：	2.29
边界扫描：	YES	总线兼容性：	I2C; USB
最大时钟频率：	33 MHz	JESD-30 代码：	S-PQFP-G100
长度：	14 mm	I/O 线路数量：	62
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.8/5 V
认证状态：	Not Qualified	RAM（字数）：	32768
ROM大小（位）：	2097152 Bits	座面最大高度：	1.6 mm
子类别：	Other uPs/uCs/Peripheral ICs	最大供电电压：	5.5 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	紫外线可擦：	N
宽度：	14 mm	Base Number Matches：	1

CY8C5488AXI-LP120 数据手册

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PSoC^®5LP: CY8C54LP Family

Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

PSoC^®5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and

a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:

■ 32-bit ARM Cortex-M3 core plus DMA controller at up to 80 MHz

■ Ultra low power with industry's widest voltage range

■ Programmable digital and analog peripherals enable custom functions

■ Flexible routing of any analog or digital peripheral function to any pin

PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable

analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and

analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.

Features

■ Operating characteristics

■ Analog peripherals

❐ Voltage range: 1.71 to 5.5 V, up to 6 power domains

❐ Temperature range (ambient) –40 to 85 °C^[1]

❐ DC to 80-MHz operation

❐ Power modes

• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz

• 2-µA sleep mode

❐ Configurable 8- to 12-bit delta-sigma ADC

❐ 12-bit SAR ADC

❐ Two 8-bit DACs

❐ Four comparators

❐ Two opamps

❐ Two programmable analog blocks, to create:

• Programmable gain amplifier (PGA)

• Transimpedance amplifier (TIA)

• Mixer

• 300-nA hibernate mode with RAM retention

❐ Boost regulator from 0.5-V input up to 5-V output

• Sample and hold circuit

■ Performance

❐ 32-bit ARM Cortex-M3 CPU, 32 interrupt inputs

❐ 24-channel direct memory access (DMA) controller

❐ CapSense^®support, up to 62 sensors

❐ 1.024 V ±1% internal voltage reference

■ Versatile I/O system

❐ 46 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)

❐ Up to eight performance I/O (SIO) pins

■ Memories

❐ Up to 256 KB program flash, with cache and security features

❐ Up to 32 KB additional flash for error correcting code (ECC)

❐ Up to 64 KB RAM

• 25 mA current sink

• Programmable input threshold and output high voltages

• Can act as a general-purpose comparator

• Hot swap capability and overvoltage tolerance

❐ Two USBIO pins that can be used as GPIOs

❐ Route any digital or analog peripheral to any GPIO

❐ LCD direct drive from any GPIO, up to 46 × 16 segments

❐ CapSense support from any GPIO

❐ 2 KB EEPROM

■ Digital peripherals

❐ Four 16-bit timer, counter, and PWM (TCPWM) blocks

❐ I²C, 1 Mbps bus speed

^❐f^Ua^Sce^B(²T^.I⁰D^c#^e1^r0^ti8^fi4^e0^d0^F3^u2^l)^l-Sus^pi^en^eg^din⁽t^Fe^Srn⁾a¹l²o^Msc^bil^pla^sto^pr^e^[2^r^]^{ipheral inter-}

❐ 20 to 24 universal digital blocks (UDB), programmable to

create any number of functions:

❐ 1.2-V to 5.5-V interface voltages, up to four power domains

■ Programming, debug, and trace

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• I²C, UART, SPI, I2S, LIN 2.0 interfaces

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generators

• Quadrature decoders

❐ JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire

viewer (SWV), and Traceport (5-wire) interfaces

❐ ARM debug and trace modules embedded in the CPU core

❐ Bootloader programming through I²C, SPI, UART, USB, and

other interfaces

• Gate-level logic functions

■ Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP

■ Programmable clocking

❐ 3- to 74-MHz internal oscillator, 2% accuracy at 3 MHz

❐ 4- to 25-MHz external crystal oscillator

❐ Internal PLL clock generation up to 80 MHz

❐ Low-power internal oscillator at 1, 33, and 100 kHz

❐ 32.768-kHz external watch crystal oscillator

❐ 12 clock dividers routable to any peripheral or I/O

■ Development support with free PSoC Creator™ tool

❐ Schematic and firmware design support

❐ Over 100 PSoC Components™ integrate multiple ICs and

system interfaces into one PSoC. Components are free

embedded ICs represented by icons. Drag and drop

component icons to design systems in PSoC Creator.

❐ Includes free GCC compiler, supports Keil/ARM MDK

compiler

❐ Supports device programming and debugging

Notes

1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. This feature on select devices only. See Ordering Information on page 116 for details.

Cypress Semiconductor Corporation

Document Number: 001-84934 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 2, 2017

12 3 4 5 6 7...126

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与CY8C5488AXI-LP120相关器件

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CY8C5488FNI-LP212T	INFINEON	获取价格	CY8C54LPxxx
CY8C5488LTI-037	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5488LTI-LP093	CYPRESS	获取价格	Multifunction Peripheral, CMOS, QFN-68
CY8C5488PVI-077	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5488PVI-103	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
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CY8C55	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)
CY8C55_11	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)
CY8C55_1106	CYPRESS	获取价格	Programmable System-on-Chip (PSoC) DC to 67 MHz operation
CY8C5566AXI-061	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)

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