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CY8C5487AXI-011 PDF预览

CY8C5487AXI-011

更新时间: 2024-11-11 06:51:51
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赛普拉斯 - CYPRESS /
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Programmable System-on-Chip (PSoC)

CY8C5487AXI-011 数据手册

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PRELIMINARY  
PSoC®5: CY8C54 Family Data Sheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC®5 is a true system level solution providing MCU, memory, analog, and digital  
peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control  
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to  
ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The  
CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,  
multi-master I2C, and CAN. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible  
routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system  
level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic  
design entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily  
accommodating last minute design changes through simple firmware updates.  
‡
Library of advanced peripherals  
• Cyclic Redundancy Check (CRC)  
• Pseudo Random Sequence (PRS) generator  
• LIN Bus 2.0  
Features  
„
32-bit ARM Cortex-M3 CPU core  
‡
DC to 80 MHz operation  
‡
Flash program memory, up to 256 KB, 100,000 write cycles,  
20 year retention, multiple security features  
• Quadrature decoder  
„
Analog peripherals (1.71V Vdda 5.5V)  
‡
‡
‡
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Up to 64 KB SRAM memory  
1.024V±0.1% internal voltage reference across -40°C to  
+85°C (14 ppm/°C)  
2 KB EEPROM memory, 1 million cycles, 20 years retention  
24 channel DMA with multilayer AHB bus access  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
‡
‡
Two SAR ADCs, each 12-bit at 1 Msps[1]  
80 MHz, 24-bit fixed point digital filter block (DFB) to  
implement FIR and IIR filters[1]  
‡
‡
‡
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Four 8-bit 8 Msps IDACs or 1 Msps VDACs  
Four comparators with 75 ns response time  
Four uncommitted opamps with 25 mA drive capability  
Four configurable multifunction analog blocks. Example con-  
figurations are PGA, TIA. Mixer and Sample and hold  
„
Low voltage, ultra low power  
‡
Wide operating voltage range: 0.5V to 5.5V  
‡
Highefficiencyboostregulatorfrom0.5Vinputto1.8Vto5.0V  
output  
‡
‡
2 mA at 6 MHz  
Low power modes including:  
„
Programming, debug, and trace  
• 300 nA hibernate mode with RAM retention and LVD  
• 2 µA sleep mode with real time clock and low voltage reset  
‡
JTAG(4wire), SerialWireDebug(SWD)(2wire), SingleWire  
Viewer (SWV), and TRACEPORT interfaces  
‡
‡
Cortex-M3 Flash Patch and Breakpoint (FPB) block  
Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-  
ates an instruction trace stream.  
Cortex-M3 Data Watchpoint and Trace (DWT) generates  
data trace information  
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be  
used for printf-style debugging  
„
Versatile I/O system  
‡
‡
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‡
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28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1]  
)
Any GPIO to any digital or analog peripheral routability  
LCD direct drive from any GPIO, up to 46x16 segments[1]  
1.2V to 5.5V I/O interface voltages, up to 4 domains  
Maskable, independent IRQ on any pin or port  
Schmitt trigger TTL inputs  
‡
‡
‡
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DWT, ETM, andITMblockscommunicatewithoff-chipdebug  
and trace systems via the SWV or TRACEPORT  
All GPIO configurable as open drain high/low, pull up/down,  
High-Z, or strong output  
Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
‡
‡
Configurable GPIO pin state at power on reset (POR)  
25 mA sink on SIO  
„
„
Precision, programmable clocking  
‡
„
Digital peripherals  
1 to 72 MHz internal ±1% oscillator (over full temperature and  
voltage range) with PLL  
4 to 33 MHz crystal oscillator for crystal PPM accuracy  
Internal PLL clock generation up to 80 MHz  
32.768 kHz watch crystal oscillator  
‡
‡
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‡
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20 to 24 programmable PLD based Universal Digital Blocks  
Full CAN 2.0b 16 RX, 8 TX buffers[1]  
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Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[1]  
Four 16-bit configurable timer, counter, and PWM blocks  
Library of standard peripherals  
Low power internal oscillator at 1 kHz, 100 kHz  
• 8, 16, 24, and 32-bit timers, counters, and PWMs  
Temperature and packaging  
‡
• SPI, UART, I2C  
-40°C to +85°C degrees industrial temperature  
48-pin SSOP, 68-pin QFN, and 100-pin TQFP package  
options  
• Many others available in catalog  
‡
Note  
1. This feature on select devices only. See Ordering Information on page 88 for details.  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Document Number: 001-55036 Rev. *A  
Revised December 03, 2009  
[+] Feedback  

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