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CY8C5466AXI-064

更新时间： 2024-11-11 09:46:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器时钟
页数 文件大小 规格书
105页 3822K
描述
Programmable System-on-Chip (PSoC?)

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CY8C5466AXI-064 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP, QFP100,.63SQ,20
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.A.3HTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：5.68
Is Samacsys：N边界扫描：NO
总线兼容性：I2C; USB最大时钟频率：25 MHz
JESD-30 代码：S-PQFP-G100长度：14 mm
I/O 线路数量：70端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
RAM（字数）：16000ROM大小（位）：524288 Bits
座面最大高度：1.6 mm子类别：Other Microprocessor ICs
最大供电电压：5.5 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
紫外线可擦：N宽度：14 mm
Base Number Matches：1

CY8C5466AXI-064 数据手册

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PRELIMINARY  
PSoC® 5: CY8C54 Family Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC® 5 is a true system level solution providing MCU, memory, analog, and digital  
peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control  
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to  
ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The  
CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,  
multimaster I2C, and CAN. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible  
routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system  
level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design  
entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily  
accommodating last minute design changes through simple firmware updates.  
‡ Library of standard peripherals  
Features  
„ 32-bit ARM Cortex-M3 CPU core  
‡ DC to 67 MHz operation  
‡ Flash program memory, up to 256 KB, 100,000 write cycles,  
20 year retention, and multiple security features  
‡ Up to 64 KB SRAM memory  
‡ 2 KB EEPROM memory, 1 million cycles, and 20 years  
retention  
‡ 24-channel DMA with multilayer AHB bus access  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs  
• SPI, UART, I2C  
• Many others available in catalog  
‡ Library of advanced peripherals  
• Cyclic redundancy check (CRC)  
• Pseudo random sequence (PRS) generator  
• LIN bus 2.0  
• Quadrature decoder  
„ Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)  
‡ 1.024 V ±1% internal voltage reference across –40 °C to  
+85 °C (128 ppm/°C)  
‡ Two SAR ADCs, each 12-bit at 1 Msps  
„ Low voltage, ultra low power  
‡ Four 8-bit 8 Msps IDACs or 1 Msps VDACs  
‡ Four comparators with 95 ns response time  
‡ Four uncommitted opamps with 25 mA drive capability  
‡ Operating voltage range: 1.8 V to 5.5 V  
‡ High efficiency boost regulator from 1.8 V input to 5.0 V  
output  
‡ 2 mA at 6 MHz  
‡ Four configurable multifunction analog blocks. Example  
configurations are PGA, TIA. Mixer and Sample and hold  
‡ Low-power modes including:  
• 2 µA sleep mode with real time clock and low voltage detect  
(LVD) interrupt  
‡ CapSense support  
„ Programming, debug, and trace  
• 300 nA hibernate mode with RAM retention  
‡ JTAG (4 wire), serial-wire debug (SWD) (2 wire), single-wire  
viewer (SWV), and TRACEPORT interfaces  
„ Versatile I/O system  
‡ Cortex-M3 flash patch and breakpoint (FPB) block  
‡ Cortex-M3 Embedded Trace Macrocell™ (ETM™)  
generates an instruction trace stream.  
‡ Cortex-M3 data watchpoint and trace (DWT) generates data  
trace information  
‡ 28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO)  
‡ Any GPIO to any digital or analog peripheral routability  
‡ LCD direct drive from any GPIO, up to 46x16 segments  
‡ CapSense® support from any GPIO[2]  
‡ 1.2 V to 5.5 V I/O interface voltages, up to four domains  
‡ Maskable, independent IRQ on any pin or port  
‡ Schmitt-trigger TTL inputs  
‡ All GPIO configurable as open drain high/low,  
pull-up/pull-down, High Z, or strong output  
‡ Cortex-M3 Instrumentation Trace Macrocell (ITM) can be  
used for printf-style debugging  
‡ DWT, ETM, andITMblockscommunicatewithoff-chipdebug  
and trace systems via the SWV or TRACEPORT  
‡ Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
‡ 25 mA sink on SIO  
„ Precision, programmable clocking  
„ Digital peripherals  
‡ 3 to 62 MHz internal oscillator over full temperature and  
‡ 20 to 24 programmable PLD based universal digital  
voltage range  
blocks (UDB)  
‡ Full CAN 2.0b 16 RX, 8 TX buffers[1]  
‡ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator  
‡ Four 16-bit configurable timer, counter, and PWM blocks  
‡ 67 MHz, 24-bit fixed point digital filter block (DFB) to  
implement FIR and IIR filters  
‡ 4 to 25 MHz crystal oscillator for crystal PPM accuracy  
‡ Internal PLL clock generation up to 67 MHz  
‡ 32.768 KHz watch crystal oscillator  
‡ Low-power internal oscillator at 1, 33, and 100 kHz  
„ Temperature and packaging  
‡ –40 °C to +85 °C degrees industrial temperature  
‡ 68-pin QFN and 100-pin TQFP package options  
Notes  
1. This feature on select devices only. See Ordering Information on page 98 for details.  
2. GPIOs with opamp outputs are not recommended for use with CapSense.  
Cypress Semiconductor Corporation  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Document Number: 001-66238 Rev. **  
Revised March 28, 2011  
[+] Feedback  
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中文翻译

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CY8C5466AXI-064 替代型号

型号 品牌 替代类型 描述 数据表
CY8C5666AXI-LP004 CYPRESS

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