CY8C42xx-BL
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
Arm®
controllers with an
Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE product
family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth® Low Energy,
also known as Bluetooth® smart, radio and subsystem (BLESS). The other features include digital programmable
logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard
communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and
in-field tuning of the design.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0 CPU with single-cycle multiply and DMA
- Up to 256 KB of flash with read accelerator
- Up to 32 KB of SRAM
• Bluetooth® LE radio and subsystem
- Bluetooth® LE 4.2 support
- 2.4-GHz RF transceiver with 50-Ω antenna drive
- Digital PHY
- Link-layer engine supporting master and slave modes
- RF output power: –18 dBm to +3 dBm
- RX sensitivity: –89 dBm
- RX current: 18.7 mA
- TX current: 15.6 mA at 0 dBm
- Received Signal Strength Indication (RSSI): 1-dB resolution
• Programmable analog
- Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes,
and ADC input buffering capability. Can operate in Deep Sleep mode.
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep mode
• Programmable digital
- Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data
path
- Infineon-provided peripheral component library, user-defined state machines, and Verilog input
• Power management
- Active mode: 1.7 mA at 3-MHz flash program execution
- Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO) on
- Hibernate mode: 150 nA with RAM retention
- Stop mode: 60 nA
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class SNR (>5:1) and liquid tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning algorithm (SmartSense)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-23053 Rev. *B
2023-03-29