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CY8C4245PVI-482 PDF预览

CY8C4245PVI-482

更新时间： 2024-11-05 18:55:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路
页数 文件大小 规格书
45页 953K
描述
Multifunction Peripheral, CMOS, PDSO28, SSOP-28

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中文翻译

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CY8C4245PVI-482 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SSOP包装说明：SSOP-28
针数：28Reach Compliance Code：compliant
ECCN代码：3A991.A.3HTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：1.53
边界扫描：NO总线兼容性：I2C; IDE; IRDA; LIN; SPI; UART
最大时钟频率：48 MHzJESD-30 代码：R-PDSO-G28
JESD-609代码：e4长度：10.2 mm
湿度敏感等级：3I/O 线路数量：24
串行 I/O 数：2端子数量：28
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
RAM（字数）：2048座面最大高度：2 mm
最大压摆率：13.8 mA最大供电电压：5.5 V
最小供电电压：1.71 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
uPs/uCs/外围集成电路类型：MULTIFUNCTION PERIPHERALBase Number Matches：1

CY8C4245PVI-482 数据手册

 浏览型号CY8C4245PVI-482的Datasheet PDF文件第2页浏览型号CY8C4245PVI-482的Datasheet PDF文件第3页浏览型号CY8C4245PVI-482的Datasheet PDF文件第4页浏览型号CY8C4245PVI-482的Datasheet PDF文件第5页浏览型号CY8C4245PVI-482的Datasheet PDF文件第6页浏览型号CY8C4245PVI-482的Datasheet PDF文件第7页 
PSoC® 4: PSoC 4200  
Family Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system  
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible  
automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital program-  
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing  
peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and  
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.  
Features  
32-bit MCU Sub-system  
Serial Communication  
■ 48-MHz ARM Cortex-M0 CPU with single cycle multiply  
■ Up to 32 kB of flash with Read Accelerator  
■ Up to 4 kB of SRAM  
■ Two independent run-time reconfigurable serial communi-  
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART  
functionality  
Timing and Pulse-Width Modulation  
Programmable Analog  
■ Four 16-bit timer/counter pulse-width modulator (TCPWM)  
blocks  
■ Two opamps with reconfigurable high-drive external and  
high-bandwidth internal drive, Comparator modes, and ADC  
input buffering capability  
■ Center-aligned, Edge, and Pseudo-random modes  
■ 12-bit, 1-Msps SAR ADC with differential and single-ended  
modes; Channel Sequencer with signal averaging  
■ Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
■ Two current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
Up to 36 Programmable GPIOs  
■ Two low-power comparators that operate in Deep Sleep mode  
■ Any GPIO pin can be CapSense, LCD, analog, or digital  
■ Drive modes, strengths, and slew rates are programmable  
Programmable Digital  
■ Four programmable logic blocks called universal digital blocks,  
(UDBs), each with 8 Macrocells and data path  
Five different packages  
■ 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and  
28-pin SSOP package  
■ Cypress-provided peripheral component library, user-defined  
state machines, and Verilog input  
■ 35-ball WLCSP package is shipped with I2C Bootloader in  
Flash  
Low Power 1.71-V to 5.5-V Operation  
■ 20-nA Stop Mode with GPIO pin wakeup  
Extended Industrial Temperature Operation  
■ Hibernate and Deep Sleep modes allow wakeup-time versus  
power trade-offs  
■ –40 °C to + 105 °C operation  
PSoC Creator Design Environment  
Capacitive Sensing  
■ Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class  
SNR (>5:1) and water tolerance  
■ Cypress-supplied software component makes capacitive  
sensing design easy  
■ Applications Programming Interface (API) component for all  
fixed-function and programmable peripherals  
■ Automatic hardware tuning (SmartSense™)  
Industry-Standard Tool Compatibility  
Segment LCD Drive  
■ After schematic entry, development can be done with  
ARM-based industry-standard development tools  
■ LCD drive supported on all pins (common or segment)  
■ Operates in Deep Sleep mode with 4 bits per pin memory  
Cypress Semiconductor Corporation  
Document Number: 001-87197 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 10, 2017  
1234567...45

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