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CY8C4246AZI-L423 PDF预览

CY8C4246AZI-L423

更新时间: 2024-11-06 00:44:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路
页数 文件大小 规格书
46页 4071K
描述
Programmable System-on-Chip

CY8C4246AZI-L423 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TQFP-48Reach Compliance Code:compliant
ECCN代码:3A991.A.3HTS代码:8542.31.00.01
风险等级:2.19边界扫描:NO
总线兼容性:I2C; IRDA; LIN; SPI; UART; USB最大时钟频率:48 MHz
JESD-30 代码:S-PQFP-G48长度:7 mm
I/O 线路数量:38端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCHRAM(字数):4096
座面最大高度:1.6 mm最大压摆率:14.5 mA
最大供电电压:5.5 V最小供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmuPs/uCs/外围集成电路类型:MULTIFUNCTION PERIPHERAL
Base Number Matches:1

CY8C4246AZI-L423 数据手册

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PSoC® 4: PSoC 4200-L Family  
Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an  
ARM® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The  
PSoC 4200-L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, program-  
mable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion,  
opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200-L products will be fully  
compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital  
subsystems allow flexibility and in-field tuning of the design.  
Features  
32-bit MCU Subsystem  
Serial Communication  
48 MHz ARM Cortex-M0 CPU with single-cycle multiply  
Up to 256 kB of flash with Read Accelerator  
Up to 32 kB of SRAM  
Four independent run-time reconfigurable serial communi-  
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART  
functionality  
USB Full-Speed device interface 12 Mbits/sec with Battery  
Charger Detect capability  
DMA engine with 32 channels  
Programmable Analog  
Two independent CAN blocks for industrial and automotive  
networking  
Four opamps that operate in Deep Sleep mode at very low  
current levels  
Timing and Pulse-Width Modulation  
All opamps have reconfigurable high current pin-drive,  
high-bandwidth internal drive, ADC input buffering, and  
Comparator modes with flexible connectivity allowing input  
connections to any pin  
Eight 16-bit timer/counter pulse-width modulator (TCPWM)  
blocks  
Center-aligned, Edge, and Pseudo-random modes  
Four current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
Two low-power comparators that operate in Deep Sleep mode  
Up to 98 Programmable GPIOs  
Programmable Digital  
124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFN  
packages  
Eight programmable logic blocks, each with 8 Macrocells and  
an 8-bit data path (called universal digital blocks or UDBs)  
Cypress-provided peripheral component library, user-defined  
state machines, and Verilog input  
Any of up to 94 GPIO pins can be CapSense, analog, or digital  
Drive modes, strengths, and slew rates are programmable  
Low Power 1.71 V to 5.5 V Operation  
PSoC Creator Design Environment  
20-nA Stop Mode with GPIO pin wakeup  
Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
Hibernate and Deep Sleep modes allow wakeup-time versus  
power trade-offs  
Capacitive Sensing  
Applications Programming Interface (API component) for all  
fixed-function and programmable peripherals  
Two Cypress Capacitive Sigma-Delta (CSD) blocks provide  
best-in-class SNR (>5:1) and water tolerance  
Industry-Standard Tool Compatibility  
Cypress-supplied software component makes capacitive  
sensing design easy  
After schematic entry, development can be done with  
ARM-based industry-standard development tools  
Automatic hardware tuning (SmartSense™)  
Segment LCD Drive  
LCD drive supported on any pin with up to a maximum of 64  
outputs (common or segment)  
Operates in Deep Sleep mode with 4 bits per pin memory  
Cypress Semiconductor Corporation  
Document Number: 001-91686 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 23, 2016  

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