PSoC® 4: PSoC 4200-L Family
Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4200-L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, program-
mable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion,
opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200-L products will be fully
compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital
subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
Serial Communication
■ 48 MHz ARM Cortex-M0 CPU with single-cycle multiply
■ Up to 256 kB of flash with Read Accelerator
■ Up to 32 kB of SRAM
■ Four independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
■ USB Full-Speed device interface 12 Mbits/sec with Battery
Charger Detect capability
■ DMA engine with 32 channels
Programmable Analog
■ Two independent CAN blocks for industrial and automotive
networking
■ Four opamps that operate in Deep Sleep mode at very low
current levels
Timing and Pulse-Width Modulation
■ All opamps have reconfigurable high current pin-drive,
high-bandwidth internal drive, ADC input buffering, and
Comparator modes with flexible connectivity allowing input
connections to any pin
■ Eight 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
■ Center-aligned, Edge, and Pseudo-random modes
■ Four current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■ Two low-power comparators that operate in Deep Sleep mode
Up to 98 Programmable GPIOs
Programmable Digital
■ 124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFN
packages
■ Eight programmable logic blocks, each with 8 Macrocells and
an 8-bit data path (called universal digital blocks or UDBs)
■ Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
■ Any of up to 94 GPIO pins can be CapSense, analog, or digital
■ Drive modes, strengths, and slew rates are programmable
Low Power 1.71 V to 5.5 V Operation
PSoC Creator Design Environment
■ 20-nA Stop Mode with GPIO pin wakeup
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
■ Applications Programming Interface (API component) for all
fixed-function and programmable peripherals
■ Two Cypress Capacitive Sigma-Delta (CSD) blocks provide
best-in-class SNR (>5:1) and water tolerance
Industry-Standard Tool Compatibility
■ Cypress-supplied software component makes capacitive
sensing design easy
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
■ Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■ LCD drive supported on any pin with up to a maximum of 64
outputs (common or segment)
■ Operates in Deep Sleep mode with 4 bits per pin memory
Cypress Semiconductor Corporation
Document Number: 001-91686 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2016
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