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CY8C4246AZI-M475 PDF预览

CY8C4246AZI-M475

更新时间: 2024-09-16 15:46:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路
页数 文件大小 规格书
42页 3776K
描述
Multifunction Peripheral, CMOS, PQFP64, TQFP-64

CY8C4246AZI-M475 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LFQFP, QFP64(UNSPEC)Reach Compliance Code:compliant
ECCN代码:3A991.A.3HTS代码:8542.31.00.01
风险等级:2.24Samacsys Description:PSoC 42xxM
地址总线宽度:边界扫描:NO
总线兼容性:I2C; SPI; UART; IRDA; IDE; LIN最大时钟频率:48 MHz
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
长度:10 mmI/O 线路数量:51
串行 I/O 数:11端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64(UNSPEC)封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
RAM(字数):8000座面最大高度:1.6 mm
最大压摆率:13.8 mA最大供电电压:5.5 V
最小供电电压:1.71 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
uPs/uCs/外围集成电路类型:MULTIFUNCTION PERIPHERALBase Number Matches:1

CY8C4246AZI-M475 数据手册

 浏览型号CY8C4246AZI-M475的Datasheet PDF文件第2页浏览型号CY8C4246AZI-M475的Datasheet PDF文件第3页浏览型号CY8C4246AZI-M475的Datasheet PDF文件第4页浏览型号CY8C4246AZI-M475的Datasheet PDF文件第5页浏览型号CY8C4246AZI-M475的Datasheet PDF文件第6页浏览型号CY8C4246AZI-M475的Datasheet PDF文件第7页 
PSoC® 4: PSoC 4200M Family  
Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an  
ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The  
PSoC 4200M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic,  
programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode,  
and standard communication and timing peripherals. The PSoC 4200M products will be fully compatible with members of the PSoC 4  
platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning  
of the design.  
Features  
32-bit MCU Subsystem  
Serial Communication  
48 MHz ARM Cortex-M0 CPU with single-cycle multiply  
Up to 128 kB of flash with Read Accelerator  
Up to 16 kB of SRAM  
Four independent run-time reconfigurable serial communi-  
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART  
functionality  
Two independent CAN blocks for industrial and automotive  
networking  
DMA engine  
Programmable Analog  
Timing and Pulse-Width Modulation  
Four opamps that operate in Deep Sleep mode at very low  
current levels  
Eight 16-bit timer/counter pulse-width modulator (TCPWM)  
blocks  
All opamps have reconfigurable high current pin-drive,  
high-bandwidth internal drive, ADC input buffering, and  
Comparator modes with flexible connectivity allowing input  
connections to any pin  
Center-aligned, Edge, and Pseudo-random modes  
Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
Four current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
Package Options  
Two low-power comparators that operate in Deep Sleep mode  
12-bit SAR ADC with 1-Msps conversion rate  
68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin  
and 44-pin TQFP packages  
Programmable Digital  
Up to 55 programmable GPIOs  
Four programmable logic blocks, each with 8 Macrocells and  
an 8-bit data path (called universal digital blocks or UDBs)  
GPIO pins can be CapSense, LCD, analog, or digital  
Drive modes, strengths, and slew rates are programmable  
Cypress-provided peripheral component library, user-defined  
state machines, and Verilog input  
Extended Industrial Temperature Operation  
Low Power 1.71 to 5.5 V Operation  
–40 °C to +105 °C operation  
20-nA Stop Mode with GPIO pin wakeup  
PSoC Creator Design Environment  
Hibernate and Deep Sleep modes allow wakeup-time versus  
power trade-offs  
Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
Capacitive Sensing  
Cypress Capacitive Sigma-Delta (CSD) technique provides  
best-in-class SNR (>5:1) and water tolerance  
Applications Programming Interface (API component) for all  
fixed-function and programmable peripherals  
Cypress-supplied software component makes capacitive  
sensing design easy  
Industry-Standard Tool Compatibility  
After schematic entry, development can be done with  
ARM-based industry-standard development tools  
Automatic hardware tuning (SmartSense™)  
Segment LCD Drive  
LCD drive supported on all pins (common or segment)  
Operates in Deep Sleep mode with 4 bits per pin memory  
Cypress Semiconductor Corporation  
Document Number: 001-93963 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 19, 2016  

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