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CY7S1061GE30-10ZXIT PDF预览

CY7S1061GE30-10ZXIT

更新时间： 2024-11-21 00:47:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
23页 1971K
描述
16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze™ and ECC

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中文翻译

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CY7S1061GE30-10ZXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSOP1,
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：10 nsJESD-30 代码：R-PDSO-G48
长度：18.4 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
Base Number Matches：1

CY7S1061GE30-10ZXIT 数据手册

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CY7S1061G/CY7S1061GE  
16-Mbit (1 M words × 16 bit) Static RAM  
with PowerSnooze™ and ECC  
16-Mbit (1  
M words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)  
To access devices with a single-chip enable input, assert the chip  
enable input (CE) LOW. To access dual chip enable devices,  
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.  
Features  
■ High speed  
❐ tAA = 10 ns  
■ Ultra-low power PowerSnooze™[1] device  
To perform data writes, assert the Write Enable (WE) input LOW,  
and provide the data and address on device data pins (I/O0  
through I/O15) and address pins (A0 through A19) respectively.  
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs  
control byte writes, and write data on the corresponding I/O lines  
to the memory location specified. BHE controls I/O8 through  
I/O15 and BLE controls I/O0 through I/O7.  
❐ Deep Sleep (DS) current IDS = 22-µA maximum  
■ Low active and standby currents  
❐ ICC = 90-mA typical  
❐ ISB2 = 20-mA typical  
To perform data reads, assert the Output Enable (OE) input and  
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,  
and 4.5 V to 5.5 V  
provide the required address on the address lines. Read data is  
accessible on the I/O lines (I/O0 through I/O15). You can perform  
byte accesses by asserting the required byte enable signal (BHE  
or BLE) to read either the upper byte or the lower byte of data  
from the specified address location.  
■ Embedded error-correcting code (ECC) for single-bit error  
correction  
■ 1.0-V data retention  
All I/Os (I/O0 through I/O15) are placed in a high-impedance state  
when the device is deselected (CE HIGH for single chip enable  
devices and CE1 HIGH and CE2 LOW for dual chip enable  
devices), or the control signals (OE, BLE, BHE) are de-asserted.  
■ Transistor-transistor logic (TTL) compatible inputs and outputs  
■ Error indication (ERR) pin to indicate 1-bit error detection and  
correction  
The device is placed in a low power Deep Sleep mode when the  
Deep Sleep pin (DS) is LOW. In this state, the device is disabled  
for normal operation and is placed in a data retention mode. The  
device can be activated by de-asserting the Deep Sleep pin (DS  
HIGH).  
■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball  
VFBGA packages  
Functional Description  
The CY7S1061G/CY7S1061GE is a high-performance CMOS  
fast static RAM organized as 1,048,576 words by 16 bits. This  
device features fast access times (10 ns) and a unique ultra-low  
power Deep Sleep mode. With Sleep mode currents as low as  
22 µA, the CY7S1061G device combines the best features of  
fast and low-power SRAM in industry-standard package options.  
The device also features embedded ECC[2]. ECC logic can  
detect and correct single-bit error in the accessed location. The  
CY7S1061GE device includes an ERR pin that signals an  
error-detection and correction event during a read cycle.  
The CY7S1061G/CY7S1061G is available in 48-pin TSOP I,  
54-pin TSOP II, and 48-ball VFBGA packages.  
For a complete list of related resources, click here.  
Product Portfolio  
Current Consumption  
Operating ICC  
Speed  
(ns)  
(mA)  
Product  
Range  
VCC Range (V)  
Standby, ISB2 (mA) Deep-Sleep Current (µA)  
f = fmax  
Typ [3] Max  
Typ [3]  
Max  
Typ [1]  
Max  
CY7S1061G18  
1.65 V–2.2 V  
2.2 V–3.6 V  
4.5–5.5 V  
15  
10  
10  
70  
90  
90  
80  
CY7S1061G(E)30 Industrial  
CY7S1061G  
110  
110  
20  
30  
8
22  
Notes  
1. Refer to AN89371 for details on PowerSnooze™ feature of this device.  
2. This device does not support automatic write-back on error detection.  
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),  
CC  
CC  
V
= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC CC CC A  
Cypress Semiconductor Corporation  
Document Number: 001-79707 Rev. *N  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 15, 2016  
1234567...23

中文翻译

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