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CY81U032X16A9A-8N4FI PDF预览

CY81U032X16A9A-8N4FI

更新时间: 2024-11-20 21:13:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
14页 227K
描述
Standard SRAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48

CY81U032X16A9A-8N4FI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:6 X 8 MM, 1 MM HEIGHT, FBGA-48针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Base Number Matches:1

CY81U032X16A9A-8N4FI 数据手册

 浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第2页浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第3页浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第4页浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第5页浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第6页浏览型号CY81U032X16A9A-8N4FI的Datasheet PDF文件第7页 
CY81U032X16A9A  
MoBL3™  
PRELIMINARY  
32M (2M x 16) SRAM  
(OE HIGH), or during a write operation (CE LOW and WE  
LOW).  
Features  
Very high speed: 70 ns  
Advanced low-power MoBL architecture  
Wide voltage range:  
Writing to the device is accomplished by taking Chip Enable  
(CE) LOW and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A20). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A20).  
VCC range: 2.3V 3.1V  
VCCQ (I/O) range: 1.7V VCC  
Ultra-low active, standby power  
Easy memory expansion with CE and OE features  
1T SRAM memory cell  
Automatic power-down when deselected  
CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) LOW and Output Enable (OE) LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. See the truth table at the back of this datasheet for a  
complete description of read and write modes.  
Functional Description[1]  
The MoBL3 is a high-performance CMOS static RAM  
organized as 2M words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL) in  
portable applications such as cellular telephones. The device  
can be put into standby mode when deselected (CE HIGH, or  
both BLE and BHE HIGH). The input/output pins (I/O0 through  
I/O15) are placed in a high-impedance state when: deselected  
(CE HIGH, or both BLE and BHE HIGH), outputs are disabled  
This SRAM has multiple power down functions. The ZZ pin will  
put the SRAM into a deep sleep mode, where the data is not  
retained in the SRAM. The Variable Address Mode allows the  
user to retain data in a section of the SRAM and reduce the  
standby current. The CY81U032X16A9A has the deep sleep  
mode disabled on power-up. The VAR register can be used to  
enable the deep sleep mode.  
The MoBL3 is available in a 48-ball FBGA package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A9  
A8  
A7  
A6  
A5  
2M x 16  
RAM Array  
I/O0I/O7  
A4  
A3  
I/O8I/O15  
A2  
A1  
A0  
COLUMN DECODER  
Refresh/Power-down  
ZZ  
Circuit  
BHE  
WE  
CE  
OE  
CE  
BLE  
Power-down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the CY application note System Design Guidelineson http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05314 Rev. **  
Revised September 11, 2002  

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