5秒后页面跳转
CY81U016X16B7A-8N4FII PDF预览

CY81U016X16B7A-8N4FII

更新时间: 2024-11-24 15:42:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
13页 204K
描述
Standard SRAM, 1MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48

CY81U016X16B7A-8N4FII 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:6 X 8 MM, 1 MM HEIGHT, FBGA-48针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:85 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e0
长度:8 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:48字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:1.8/2 V
认证状态:Not Qualified座面最大高度:1 mm
最大待机电流:0.00006 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:0.015 mA
最大供电电压 (Vsup):2.25 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN LEAD端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:6 mm
Base Number Matches:1

CY81U016X16B7A-8N4FII 数据手册

 浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第2页浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第3页浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第4页浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第5页浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第6页浏览型号CY81U016X16B7A-8N4FII的Datasheet PDF文件第7页 
CY81U016X16B7A  
MoBL3™  
PRELIMINARY  
16M (1M x 16) SRAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) LOW and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A19). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A19).  
Features  
Very high speed: 85 ns  
Advanced low-power MoBL® architecture  
Wide voltage range:  
VCC range: 1.7V 2.25V  
VCCQ (I/O) range: 1.7V VCC  
Reading from the device is accomplished by taking Chip  
Enable (CE) LOW and Output Enable (OE) LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. See the truth table at the back of this datasheet for a  
complete description of read and write modes.  
Ultra-low active, standby power  
Easy memory expansion with CE and OE features  
1T SRAM memory cell  
Automatic power-down when deselected  
CMOS for optimum speed/power  
Functional Description[1]  
This SRAM has multiple power down functions. The ZZ pin will  
put the SRAM into a deep sleep mode, where the data is not  
retained in the SRAM. The Variable Address Mode allows the  
user to retain data in a section of the SRAM and reduce the  
standby current. The CY81U016X16B7A has the deep sleep  
mode enabled on Power up. The VAR register can be used to  
disable the deep sleep mode.  
The CY81U016X16B7A MoBL3  
is a high-performance  
CMOS static RAM organized as 1M words by 16 bits. This  
device features advanced circuit design to provide ultra-low  
active current. This is ideal for providing More Battery Life™  
(MoBL) in portable applications such as cellular telephones.  
The device can be put into standby mode when deselected  
(CE HIGH, or both BLE and BHE HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE HIGH, or both BLE and BHE HIGH),  
outputs are disabled (OE HIGH), or during a write operation  
(CE LOW and WE LOW).  
The CY81U016X16B7A MoBL3 is available in a 48-ball FBGA  
package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A10  
9
A8  
A7  
A6  
A5  
A4  
1M x 16  
RAM Array  
I/O0I/O7  
A3  
A2  
I/O8I/O15  
A1  
A0  
COLUMN DECODER  
ZZ  
Refresh/Power-down  
Circuit  
BHE  
WE  
CE  
OE  
CE  
BLE  
Power-down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the CY application note System Design Guidelineson http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05310 Rev. **  
Revised September 10, 2002  

与CY81U016X16B7A-8N4FII相关器件

型号 品牌 获取价格 描述 数据表
CY81U032X16A9A-7N4FI CYPRESS

获取价格

Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY81U032X16A9A-8N4FI CYPRESS

获取价格

Standard SRAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY82C597 CYPRESS

获取价格

Multifunction Peripheral, CMOS, PQFP160
CY82C597-NC CYPRESS

获取价格

Multifunction Peripheral, CMOS, PQFP16, PLASTIC, QFP-160
CY82C599NCR CYPRESS

获取价格

PCI Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160
CY82C599NCT CYPRESS

获取价格

PCI Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160
CY82C690-10C CYPRESS

获取价格

Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208
CY82C690-NC ETC

获取价格

Data Path Controller
CY82C691 CYPRESS

获取价格

Cache Controller, CMOS, PQFP208, PLASTIC, QFP-208
CY82C691-NC CYPRESS

获取价格

PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208