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CY7C43683-12AC PDF预览

CY7C43683-12AC

更新时间: 2024-11-24 15:41:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
28页 565K
描述
FIFO, 16KX36, 9ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128

CY7C43683-12AC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.85
最长访问时间:9 ns其他特性:MAILBOX; RETRANSMIT
最大时钟频率 (fCLK):83 MHz周期时间:12 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:589824 bit
内存集成电路类型:OTHER FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.1 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

CY7C43683-12AC 数据手册

 浏览型号CY7C43683-12AC的Datasheet PDF文件第2页浏览型号CY7C43683-12AC的Datasheet PDF文件第3页浏览型号CY7C43683-12AC的Datasheet PDF文件第4页浏览型号CY7C43683-12AC的Datasheet PDF文件第5页浏览型号CY7C43683-12AC的Datasheet PDF文件第6页浏览型号CY7C43683-12AC的Datasheet PDF文件第7页 
CY7C43623  
CY7C43633/CY7C43643  
CY7C43663/CY7C43683  
PRELIMINARY  
256/512/1K/4K/16K x36 Unidirectional  
Synchronous FIFO w/ Bus Matching  
• Fully asynchronous and simultaneous read and write  
operation permitted  
Features  
• High-speed, low-power, Unidirectional, first-in first-out  
(FIFO) memories w/ bus matching capabilities  
• 256x36 (CY7C43623)  
• Mailbox bypass register for each FIFO  
• Parallel and Serial Programmable Almost-Full and Al-  
most-Empty flags  
• 512x36 (CY7C43633)  
• Retransmit function  
• 1Kx36 (CY7C43643)  
• 4Kx36 (CY7C43663)  
• Standard or FWFT mode user selectable  
• Partial Reset  
• 16Kx36 (CY7C43683)  
• 0.35-micron CMOS for optimum speed/power  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• High-speed 83-MHz operation (12 ns read/write cycle  
times)  
• Pin-compatible, feature enhanced, density upgrade to  
IDT723623/33/43 family  
• Low power  
• Easily expandable in width and depth  
— I = 100 mA  
CC  
— I = 5 mA  
SB  
Logic Block Diagram  
MBF1  
CLKA  
Mail 1  
Register  
CSA  
Port-A  
Control  
W/RA  
CLKB  
CSB  
Logic  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
ENA  
Port-B  
Control  
Logic  
W/RB  
ENB  
MBA  
RT  
MBB  
BE  
BM  
SIZE  
FIFO,  
MRS1  
MRS2  
Write  
Pointer  
Read  
Pointer  
Mail1  
Mail2  
Reset  
Logic  
PRS  
FF/IR  
AF  
EF/OR  
AE  
Status  
Flag Logic  
36  
B
0–35  
SPM  
FS0/SD  
FS1/SEN  
Timing  
Mode  
Programmable Flag  
Offset Registers  
BE/FWFT  
36  
A
0–35  
Mail 2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 2, 1998  

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