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CY7C43646V-15AC PDF预览

CY7C43646V-15AC

更新时间: 2024-11-24 14:41:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
38页 788K
描述
Bi-Directional FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128

CY7C43646V-15AC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
针数:128Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.56Is Samacsys:N
最长访问时间:10 ns其他特性:MAIL BOX; RETRANSMIT
最大时钟频率 (fCLK):67 MHz周期时间:15 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:36864 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
功能数量:1端子数量:128
字数:1024 words字数代码:1000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.012 A
子类别:FIFOs最大压摆率:0.06 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CY7C43646V-15AC 数据手册

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V
CY7C43646V  
PRELIMINARY  
CY7C43666V/CY7C43686V  
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO  
• Fully asynchronous and simultaneous read and write  
operation permitted  
Features  
• 3.3V high-speed, low-power, first-in first-out (FIFO)  
memoriesw/threeindependentports(onebidirectional  
x36, and two unidirectional x18)  
• 1K x36/x18x2 (CY7C43646V)  
• 4K x36/x18x2 (CY7C43666V)  
• 16K x36/x18x2 (CY7C43686V)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed 67-MHz operation (15 ns read/write cycle  
times)  
• Low power  
• Mailbox bypass register for each FIFO  
• Parallel and Serial Programmable Almost-Full and Al-  
most-Empty flags  
• Retransmit function  
• Standard or FWFT mode user selectable  
• Partial Reset  
• Big or little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• 3.3V pin-compatible, feature enhanced, density up-  
grade to IDT723626/36/46 family  
— I = 60 mA  
CC  
• Easily expandable in width and depth  
— I = 5.0 mA  
SB  
Logic Block Diagram  
MBF1  
CLKA  
Mail 1  
Register  
CSA  
Port-A  
Control  
W/RA  
Logic  
B
1K/4K/16K  
x36  
Dual Ported  
Memory  
0–17  
ENA  
CLKB  
MBA  
RT2  
RENB  
Port-B  
Control  
CSB  
Logic  
SIZEB  
MBB  
RTI  
MRS1  
FIFO1,  
Mail 1  
Reset  
Logic  
Read  
Pointer  
Write  
Pointer  
PRS1  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
Common  
Port Logic  
(B and C)  
BE  
SPM  
FS0/SD  
Timing  
Mode  
Programmable Flag  
Offset Registers  
FS1/SEN  
BE/FWFT  
A
0–35  
Status  
Flag Logic  
FFC/IRC  
AFC  
EFA/ORA  
AEA  
FIFO2,  
Mail 2  
Reset  
Logic  
MRS2  
PRS2  
Write  
Pointer  
Read  
Pointer  
C
0–17  
1K/4K/16K  
x36  
Dual Ported  
Memory  
CLKC  
Port-C  
Control  
Logic  
WENC  
SIZEC  
MBC  
Mail 2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 2, 1998  

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