Datasheet > CY7C43662AV-15AC

CY7C43662AV-15AC

更新时间： 2024-11-23 22:11:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
30页	483K
描述
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO

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中文翻译

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数据手册

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CY7C43662AV-15AC 数据手册

CY7C43642AV

CY7C43662AV

CY7C43682AV

3.3V 1K/4K/16K x36 x2 Bidirectional

Synchronous FIFO

• Low power

— I_CC= 60 mA

— I_SB= 10 mA

Features

• 3.3V high-speed, low-power, bidirectional, First-In

First-Out (FIFO) memories

• Fully asynchronous and simultaneous Read and Write

operations permitted

• Mailbox bypass register for each FIFO

• Parallel Programmable Almost Full and Almost Empty

flags

• Retransmit function

• 1K ×36 ×2 (CY7C43642AV)

• 4K x36 x2 (CY7C43662AV)

• 16K x36 x2 (CY7C43682AV)

• 0.25-micron CMOS for optimum speed/power

• High-speed 133-MHz operation (7.5-ns Read/Write

cycle times)

• Standard or FWFT user-selectable mode

• 120-pin TQFP package

• Easily expandable in width and depth

Logic Block Diagram

MBF1

CLKA

Mail1

CSA

Port A

Control

W/RA

CLKB

Logic

1K/4K/16K

× 36

Dual Ported

Memory

(FIFO1)

ENA

CSB

Port B

Control

Logic

MBA

RT2

W/RB

ENB

MBB

RT1

MRST1

FIFO1,

Mail1

Reset

Write

Pointer

Read

Pointer

Logic

FFA/IRA

Status

Flag Logic

EFB/ORB

AEB

AFA

0–35

Timing

Mode

Programmable

Flag Offset

Registers

FS0

FS1

FWFT/STAN

0–35

Status

Flag Logic

FFB/IRB

AFB

EFA/ORA

AEA

Read

Pointer

Write

Pointer

MRST2

FIFO2,

Mail2

Reset

Logic

1K/4K/16K

× 36

Dual Ported

Memory

(FIFo2)

Mail2

MBF2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06020 Rev. *C

Revised December 26, 2002

12 3 4 5 6 7...30

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与CY7C43662AV-15AC相关器件

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CY7C43662AV-7AC	CYPRESS	获取价格	3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
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CY7C43663AV-15AC	CYPRESS	获取价格	3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching