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CY7C43666 PDF预览

CY7C43666

更新时间: 2024-11-24 04:53:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
39页 641K
描述
1K/4K/16K x36/x18/x2 Tri Bus FIFO

CY7C43666 数据手册

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CY7C43666 CY7C436461K/4K/16K x36/x18/x2 Tri Bus FIFO  
CY7C43646  
CY7C43666  
CY7C43686  
1K/4K/16K x36/x18/x2 Tri Bus FIFO  
• Fully asynchronous and simultaneous read and write  
operation permitted  
• Mailbox bypass register for each FIFO  
Features  
• High-speed, low-power, first-in first-out (FIFO) memo-  
ries w/ three independent ports (one bidirectional x36,  
and two unidirectional x18)  
• 1K x36/x18x2 (CY7C43646)  
• 4K x36/x18x2 (CY7C43666)  
• 16K x36/x18x2 (CY7C43686)  
• Parallel and Serial Programmable Almost Full and  
Almost Empty flags  
• Retransmit function  
• Standard or FWFT mode user-selectable  
• Partial Reset  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• Easily expandable in width and depth  
• 0.35-micron CMOS for optimum speed/power  
• High speed 133-MHz operation (7.5-ns read/write  
cycle times)  
• Low power  
— ICC= 100 mA  
— ISB= 10 mA  
Logic Block Diagram  
MBF1  
CLKA  
Mail1  
CSA  
Register  
Port A  
Control  
Logic  
W/RA  
ENA  
MBA  
RT2  
1K/4K/16K  
x36  
Dual Ported  
Memory  
B
017  
CLKB  
RENB  
CSB  
SIZEB  
MBB  
RTI  
Port B  
Control  
Logic  
MRS1  
PRS1  
FIFO1,  
Mail1  
Reset  
Logic  
Read  
Pointer  
Write  
Pointer  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
Common  
BE  
Port Logic  
(B and C)  
SPM  
FS0/SD  
FS1/SEN  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
BE/FWFT  
A
035  
Status  
Flag Logic  
FFC/IRC  
AFC  
EFA/ORA  
AEA  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
Write  
Pointer  
Read  
Pointer  
C
017  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
CLKC  
WENC  
Port C  
Control  
Logic  
SIZEC  
MBC  
Mail2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-06023 Rev. *C  
Revised September 26, 2003  

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