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CY7C43662AV-7AC PDF预览

CY7C43662AV-7AC

更新时间: 2024-11-23 22:11:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
30页 483K
描述
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO

CY7C43662AV-7AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-120
针数:120Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:6 ns
其他特性:MAILBOX; RETRANSMIT最大时钟频率 (fCLK):133 MHz
周期时间:7.5 nsJESD-30 代码:S-PQFP-G120
JESD-609代码:e0长度:14 mm
内存密度:147456 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36功能数量:1
端子数量:120字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.012 A子类别:FIFOs
最大压摆率:0.06 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C43662AV-7AC 数据手册

 浏览型号CY7C43662AV-7AC的Datasheet PDF文件第2页浏览型号CY7C43662AV-7AC的Datasheet PDF文件第3页浏览型号CY7C43662AV-7AC的Datasheet PDF文件第4页浏览型号CY7C43662AV-7AC的Datasheet PDF文件第5页浏览型号CY7C43662AV-7AC的Datasheet PDF文件第6页浏览型号CY7C43662AV-7AC的Datasheet PDF文件第7页 
CY7C43642AV  
CY7C43662AV  
CY7C43682AV  
3.3V 1K/4K/16K x36 x2 Bidirectional  
Synchronous FIFO  
• Low power  
— ICC = 60 mA  
— ISB = 10 mA  
Features  
• 3.3V high-speed, low-power, bidirectional, First-In  
First-Out (FIFO) memories  
• Fully asynchronous and simultaneous Read and Write  
operations permitted  
• Mailbox bypass register for each FIFO  
• Parallel Programmable Almost Full and Almost Empty  
flags  
• Retransmit function  
• 1K ×36 ×2 (CY7C43642AV)  
• 4K x36 x2 (CY7C43662AV)  
• 16K x36 x2 (CY7C43682AV)  
• 0.25-micron CMOS for optimum speed/power  
• High-speed 133-MHz operation (7.5-ns Read/Write  
cycle times)  
• Standard or FWFT user-selectable mode  
• 120-pin TQFP package  
• Easily expandable in width and depth  
Logic Block Diagram  
MBF1  
CLKA  
Mail1  
Register  
CSA  
Port A  
Control  
W/RA  
CLKB  
Logic  
1K/4K/16K  
× 36  
Dual Ported  
Memory  
(FIFO1)  
ENA  
CSB  
Port B  
Control  
Logic  
MBA  
RT2  
W/RB  
ENB  
MBB  
RT1  
MRST1  
FIFO1,  
Mail1  
Reset  
Write  
Pointer  
Read  
Pointer  
Logic  
FFA/IRA  
Status  
Flag Logic  
EFB/ORB  
AEB  
AFA  
B
035  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
FS0  
FS1  
FWFT/STAN  
A
035  
Status  
Flag Logic  
FFB/IRB  
AFB  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
MRST2  
FIFO2,  
Mail2  
Reset  
Logic  
1K/4K/16K  
× 36  
Dual Ported  
Memory  
(FIFo2)  
Mail2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06020 Rev. *C  
Revised December 26, 2002  

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