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CY7C43662-12AC PDF预览

CY7C43662-12AC

更新时间: 2024-11-24 15:30:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
31页 643K
描述
Bi-Directional FIFO, 4KX36, 9ns, Synchronous, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120

CY7C43662-12AC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-120针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:9 ns其他特性:MAIL BOX; RETRANSMIT
最大时钟频率 (fCLK):83 MHz周期时间:12 ns
JESD-30 代码:S-PQFP-G120JESD-609代码:e0
长度:14 mm内存密度:147456 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:120字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.4 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

CY7C43662-12AC 数据手册

 浏览型号CY7C43662-12AC的Datasheet PDF文件第2页浏览型号CY7C43662-12AC的Datasheet PDF文件第3页浏览型号CY7C43662-12AC的Datasheet PDF文件第4页浏览型号CY7C43662-12AC的Datasheet PDF文件第5页浏览型号CY7C43662-12AC的Datasheet PDF文件第6页浏览型号CY7C43662-12AC的Datasheet PDF文件第7页 
CY7C43622  
CY7C43632/CY7C43642  
CY7C43662/CY7C43682  
PRELIMINARY  
256/512/1K/4K/16K x36 x2 Bidirectional  
Synchronous FIFO  
• Fully asynchronous and simultaneous read and write  
operation permitted  
Features  
• High-speed, low-power, bidirectional, first-in first-out  
(FIFO) memories  
• 256x36x2 (CY7C43622)  
• Mailbox bypass register for each FIFO  
• Parallel Programmable Almost-Full and Almost-Empty  
flags  
• 512x36x2 (CY7C43632)  
• Retransmit function  
• 1Kx36x2 (CY7C43642)  
• 4Kx36x2 (CY7C43662)  
• Standard or FWFT mode user selectable  
• 120-pin TQFP packaging  
• 16Kx36x2 (CY7C43682)  
• 0.35-micron CMOS for optimum speed/power  
• Pin-compatible, feature enhanced, density upgrade to  
IDT723622/32/42 family  
• Easily expandable in width and depth  
• High speed 83-MHz operation (12 ns read/write cycle  
times)  
• Low power  
— I = 100 mA  
CC  
— I = 5 mA  
SB  
Logic Block Diagram  
MBF1  
CLKB  
CLKA  
Mail 1  
Register  
CSA  
Port-A  
Control  
Logic  
W/RA  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
ENA  
CSB  
Port-B  
Control  
Logic  
W/RB  
MBA  
RT2  
ENB  
MBB  
RT1  
MRS1  
FIFO1,  
Mail 1  
Reset  
Logic  
Write  
Pointer  
Read  
Pointer  
PRS1  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
B
SPM  
FS0/SD  
FS1/SEN  
0–35  
Timing  
Mode  
Programmable Flag  
Offset Registers  
FWFT/STAN  
A
0–35  
Status  
Flag Logic  
FFB/IRB  
AFB  
EFA/ORA  
AEA  
Read  
Write  
Pointer  
Pointer  
MRS2  
PRS2  
FIFO2,  
Mail 2  
Reset  
Logic  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
Mail 2  
Register  
MBF2  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Cypress Semiconductor Corporation  
September 14, 1998  

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