Datasheet > CY7C4275V-25JC

CY7C4275V-25JC

更新时间： 2024-02-26 21:15:50

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
19页	364K
描述
FIFO, 32KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
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CY7C4275V-25JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, LCC-68
针数：	68	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.83	最长访问时间：	15 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	40 MHz
周期时间：	25 ns	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	长度：	24.2316 mm
内存密度：	589824 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	功能数量：	1
端子数量：	68	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC68,1.0SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大待机电流：	0.002 A
子类别：	FIFOs	最大压摆率：	0.03 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	24.2316 mm
Base Number Matches：	1

CY7C4275V-25JC 数据手册

fax id: 5422

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

PRELIMINARY

8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs

Features

Functional Description

The CY7C4255/65/75/85V are high-speed, low-power, first-in

first-out (FIFO) memories with clocked read and write interfac-

es. All are 18 bits wide and are pin/functionally compatible to

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 8K x 18 (CY7C4255V)

• 16K x 18 (CY7C4265V)

the

CY7C42X5V Synchronous FIFO

family. The

CY7C4255/65/75/85V can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety of

data buffering needs, including high-speed data acquisition, multipro-

cessor interfaces, and communications buffering.

• 32K x 18 (CY7C4275V)

• 64K x 18 (CY7C4285V)

• 0.35 micron CMOS for optimum speed/power

• High-speed 67-MHz operation (15 ns read/write cycle

times)

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

• Low power

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-running read clock (RCLK) and a read

enable pin (REN). In addition, the CY7C4255/65/75/85V have an

output enable pin (OE). The read and write clocksmay be tied togeth-

er for single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock frequencies

up to 67 MHz are achievable.

= 30 mA

= 3 mA

—

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, Half Full, and programmable Almost Empty

and Almost Full status flags

• Retransmit function

• Output Enable (OE pin

)

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• 68-pin PLCC and 64-pin 10x10 STQFP

• Pin-compatible density upgrade to

CY7C42X5V-JC/ASC families

• Pin-compatible 3.3V solutions for CY7C4255/65/75/85

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V and the FL pin of all the remaining devic-

es should be tied to V

0 – 17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

High

Density

Dual-Port

RAM Array

FLAG

LOGIC

PAE

PAF

8Kx9

16Kx9

32Kx9

64Kx9

SMODE

WRITE

POINTER

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

0 – 17

RXO

4275V–1

RCLK

REN

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

November 6, 1997 - Revised February 26, 1998

12 3 4 5 6 7...19

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与CY7C4275V-25JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4275V-25JCR	CYPRESS	获取价格	FIFO, 32KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275V-25JCT	CYPRESS	获取价格	FIFO, 32KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4281	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281_05	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-10JC	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-10JI	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-10JIT	CYPRESS	获取价格	FIFO, 64KX9, 8ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4281-15JC	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-25JC	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-25JCR	CYPRESS	获取价格	暂无描述

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