Datasheet > CY7C4282-25ASC

CY7C4282-25ASC

更新时间： 2024-02-20 15:44:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
16页	209K
描述
64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion

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技术参数
数据手册

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CY7C4282-25ASC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	10 X 10 MM, TQFP-64	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.85
最长访问时间：	15 ns	其他特性：	RETRANSMIT
最大时钟频率 (fCLK)：	40 MHz	周期时间：	25 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	内存密度：	589824 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
功能数量：	1	端子数量：	64
字数：	65536 words	字数代码：	64000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX9
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP64,.47SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.002 A	子类别：	FIFOs
最大压摆率：	0.045 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

CY7C4282-25ASC 数据手册

CY7C4282

CY7C4292

64K/128K x 9 Deep Sync FIFOs with

Retransmit and Depth Expansion

Features

Functional Description

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64K × 9 (CY7C4282)

• 128K × 9 (CY7C4292)

• 0.5-micron CMOS for optimum speed/power

• High-speed, near-zero latency (true dual-ported

memory cell), 100-MHz operation (10-ns read/write

cycle times)

The CY7C4282/CY7C4292 are high-speed, low-power, FIFO

memories with clocked read and write interfaces. All devices

are nine bits wide. The CY7C4282/CY7C4292 can be

cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, video

and communications buffering.

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and a

write-enable pin (WEN).

• Low power

— I_CC=40 mA

— I_SB= 2 mA

• Fully asynchronous and simultaneous read and write

operation

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Empty, Full, and Programmable Almost Empty and

Almost Full status flags

• TTL-compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width-Expansion Capability

• Depth-Expansion Capability through token-passing

scheme (no external logic required)

Depth expansion is possible using the cascade input (XI),

cascade output (XO), and First Load (FL) pins. The XO pin is

connected to the XI pin of the next device, and the XO pin of

the last device should be connected to the XI pin of the first

device. The FL pin of the first device is tied to VSS and the FL

pin of all the remaining devices should be tied to V_CC

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C4282/92 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

• 64-pin 10 × 10 STQFP

D_0-8

Logic Block Diagram

INPUT

WCLK WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

PAE

PAF/XO

Dual Port

RAM Array

64K x 9

WRITE

POINTER

128K x 9

READ

POINTER

RESET

LOGIC

THREE-STATE

OUTPUT REGISTER

FL/RT

READ

CONTROL

EXPANSION

LOGIC

XI/LD

PAF/XO

0 −

RCLK REN

Cypress Semiconductor Corporation

Document #: 38-06009 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 21, 2003

12 3 4 5 6 7...16

中文翻译

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与CY7C4282-25ASC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4282-25ASI	CYPRESS	获取价格	FIFO, 64KX9, 15ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, TQFP-64
CY7C428-25DC	CYPRESS	获取价格	FIFO, 2KX9, 25ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-25DI	CYPRESS	获取价格	FIFO, 2KX9, 25ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-25DMB	CYPRESS	获取价格	256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C428-25PC	ROCHESTER	获取价格	2K X 9 OTHER FIFO, 25 ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28
CY7C4282V	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V_03	CYPRESS	获取价格	64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion
CY7C4282V-10ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V-15ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V-15ASI	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion

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