Datasheet > CY7C4282V-25ASC

CY7C4282V-25ASC

更新时间： 2024-01-05 03:57:20

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
15页	240K
描述
64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion

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中文翻译

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技术参数
数据手册

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CY7C4282V-25ASC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64
针数：	64	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.85	最长访问时间：	15 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	40 MHz
周期时间：	25 ns	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
内存密度：	589824 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	9	功能数量：	1
端子数量：	64	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP64,.47SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.006 A
子类别：	FIFOs	最大压摆率：	0.025 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

CY7C4282V-25ASC 数据手册

CY7C4282V

CY7C4292V

64K/128Kx9 Low Voltage Deep Sync FIFOs

w/ Retransmit & Depth Expansion

Features

Functional Description

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64K x 9 (CY7C4282V)

• 128K x 9 (CY7C4292V)

The CY7C4282V/92V are high-speed, low-power, first-in first-

out (FIFO) memories with clocked read and write interfaces.

All devices are 9 bits wide. The CY7C4282V/92V can be cas-

caded to increase FIFO depth. Programmable features include

Almost Full/Almost Empty flags. These FIFOs provide solutions

for a wide variety of data buffering needs, including high-speed data

acquisition, multiprocessor interfaces, video and communications

buffering.

• 0.35 micron CMOS for optimum speed/power

• High-speed, Near Zero Latency (True Dual-Ported

Memory Cell), 100-MHz operation (10 ns read/write

cycle times)

These FIFOs have 9-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a Write Enable

pin (WEN).

• Low power

= 25 mA

= 6 mA

—

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and Programmable Almost Empty and Al-

most Full status flags

Depth expansion is possible using the Cascade Input (XI), Cas-

cade Output (XO), and First Load (FL) pins. The XO pin is connected

to the XI pin of the next device, and the XO pin of the last device

should be connected to the XI pin of the first device. The FL pin of the

• Retransmit function

first device is tied to V and the FL pin of all the remaining devices

Output Enable (OE pin

•

)

should be tied to V

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability through token-passing

scheme (no external logic required)

• 64-pin 10x10 STQFP

• Pin-compatible 3.3V solution for CY7C4282/92

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running Read

Clock (RCLK) and a Read Enable pin (REN). In addition, the

CY7C4282V/92V have an Output Enable pin (OE). The read

and write clocks may be tied together for single-clock operation

or the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 67 MHz are

achievable.

0 −

Logic

Diagram

Block

INPUT

WCLK WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

PAE

Dual Port

RAM Array

PAF/XO

64K x 9

WRITE

POINTER

128K x 9

READ

POINTER

RESET

LOGIC

THREE-STATE

OUTPUT REGISTER

FL/RT

XI/LD

READ

CONTROL

EXPANSION

LOGIC

PAF/XO

0 −

RCLK REN

4282V–1

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 18, 1999

12 3 4 5 6 7...15

中文翻译

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与CY7C4282V-25ASC相关器件

型号	品牌	获取价格	描述	数据表
CY7C428-30DC	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DI	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DMB	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DMB	ROCHESTER	获取价格	2K X 9 OTHER FIFO, 30 ns, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30PI	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
CY7C428-40DC	CYPRESS	获取价格	FIFO, 2KX9, 40ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-40DI	ETC	获取价格	x9 Asynchronous FIFO
CY7C4285	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs
CY7C4285-10ASC	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs
CY7C4285-10ASI	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs

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