Datasheet > CY7C4285V-10ASC

CY7C4285V-10ASC

更新时间： 2024-01-06 12:11:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
20页	284K
描述
32K/64Kx18 Low Voltage Deep Sync FIFOs

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技术参数
数据手册

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CY7C4285V-10ASC 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.72
最长访问时间：	8 ns	其他特性：	RETRANSMIT
周期时间：	10 ns	JESD-30 代码：	S-PQFP-G64
长度：	10 mm	内存密度：	1179648 bit
内存宽度：	18	功能数量：	1
端子数量：	64	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	认证状态：	COMMERCIAL
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

CY7C4285V-10ASC 数据手册

285V

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

32K/64Kx18 Low Voltage Deep Sync FIFOs

Features

Functional Description

The CY7C4255/65/75/85V are high-speed, low-power, first-in

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 8K x 18 (CY7C4255V)

• 16K x 18 (CY7C4265V)

first-out (FIFO) memories with clocked read and write interfac-

es. All are 18 bits wide and are pin/functionally compatible to

the CY7C42X5V Synchronous FIFO family. The

CY7C4255/65/75/85V can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety of

data buffering needs, including high-speed data acquisition, multipro-

cessor interfaces, and communications buffering.

• 32K x 18 (CY7C4275V)

• 64K x 18 (CY7C4285V)

• 0.35 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power

— I_CC= 30 mA

— I_SB= 4 mA

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-running read clock (RCLK) and a read

enable pin (REN). In addition, the CY7C4255/65/75/85V have an

output enable pin (OE). The read and write clocks may be tied togeth-

er for single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock frequencies

up to 67 MHz are achievable.

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

• Retransmit function

• Output Enable (OE) pin

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• 64-pin 10x10 STQFP

• Pin-compatible density upgrade to CY7C42X5V-ASC

families

• Pin-compatible 3.3V solutions for CY7C4255/65/75/85

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V_SSand the FL pin of all the remaining devic-

es should be tied to V_CC

0 – 17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

High

Density

Dual-Port

RAM Array

FLAG

LOGIC

PAE

PAF

SMODE

8Kx9

16Kx9

32Kx9

64Kx9

WRITE

POINTER

READ

POINTER

RESET

LOGIC

FL/RT

THREE-STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

0 – 17

RXO

4275V–1

RCLK

REN

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06012 Rev. *A

Revised December 26, 2002

12 3 4 5 6 7...20

中文翻译

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与CY7C4285V-10ASC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4285V-15ASC	ETC	获取价格	x18 Synchronous FIFO
CY7C4285V-15ASCT	CYPRESS	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-
CY7C4285V-15ASI	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4285V-15ASXC	CYPRESS	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT,
CY7C4285V-15JCT	CYPRESS	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4285V-15JIR	CYPRESS	获取价格	FIFO, 64KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4285V-15JIT	CYPRESS	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4285V-25ASC	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4285V-25JC	CYPRESS	获取价格	FIFO, 64KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4285V-25JCR	CYPRESS	获取价格	FIFO, 64KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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