Datasheet > CY7C4282V_03

CY7C4282V_03

更新时间： 2024-09-28 05:09:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
15页	214K
描述
64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion

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CY7C4282V_03 数据手册

CY7C4282V

CY7C4292V

64K/128K x 9 Low-Voltage Deep Sync FIFOs

with Retransmit and Depth Expansion

Features

Functional Description

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64K × 9 (CY7C4282V)

• 128K × 9 (CY7C4292V)

The CY7C4282V/92V are high-speed, low-power, FIFO

memories with clocked read and write interfaces. All devices

are nine bits wide. The CY7C4282V/92V can be cascaded to

increase FIFO depth. Programmable features include Almost

Full/Almost Empty flags. These FIFOs provide solutions for a

wide variety of data buffering needs, including high-speed data

acquisition, multiprocessor interfaces, video and communica-

tions buffering.

• 0.35 micron CMOS for optimum speed/power

• High-speed, Near-Zero Latency (True Dual-Ported

Memory Cell), 100-MHz operation (10 ns read/write

cycle times)

• Low power

— I_CC= 25 mA

— I_SB= 6 mA

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and a Write

Enable pin (WEN).

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and Programmable Almost Empty and

Almost Full status flags

• Retransmit function

• Output Enable (OE) pin

Depth expansion is possible using the Cascade Input (XI),

Cascade Output (XO), and First Load (FL) pins. The XO pin is

connected to the XI pin of the next device, and the XO pin of

the last device should be connected to the XI pin of the first

device. The FL pin of the first device is tied to VSS and the FL

pin of all the remaining devices should be tied to VCC

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability through token-passing

scheme (no external logic required)

• 64-pin 10 × 10 STQFP

• Pin-compatible 3.3V solution for CY7C4282/92

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running Read

Clock (RCLK) and a Read Enable pin (REN). In addition, the

CY7C4282V/92V have an Output Enable pin (OE). The read

and write clocks may be tied together for single-clock

operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to

67 MHz are achievable.

0–8

Logic

Diagram

Block

INPUT

WCLK WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

PAE

Dual Port

RAM Array

PAF/XO

64K x 9

128K x 9

WRITE

POINTER

READ

POINTER

RESET

LOGIC

THREE-STATE

OUTPUT REGISTER

FL/RT

XI/LD

READ

CONTROL

EXPANSION

LOGIC

PAF/XO

0 −

RCLK REN

Cypress Semiconductor Corporation

Document #: 38-06014 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 22, 2003

12 3 4 5 6 7...15

中文翻译

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与CY7C4282V_03相关器件

型号	品牌	获取价格	描述	数据表
CY7C4282V-10ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V-15ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V-15ASI	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4282V-25ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C428-30DC	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DI	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DMB	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30DMB	ROCHESTER	获取价格	2K X 9 OTHER FIFO, 30 ns, CDIP28, 0.600 INCH, CERDIP-28
CY7C428-30PI	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
CY7C428-40DC	CYPRESS	获取价格	FIFO, 2KX9, 40ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28

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