Datasheet > 存储 > FIFO> CY7C4281-10JIT

CY7C4281-10JIT

更新时间： 2024-02-13 00:38:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
16页	200K
描述
FIFO, 64KX9, 8ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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技术参数
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CY7C4281-10JIT 技术参数

生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	QCCJ,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.79
Is Samacsys：	N	最长访问时间：	8 ns
周期时间：	10 ns	JESD-30 代码：	R-PQCC-J32
长度：	13.97 mm	内存密度：	589824 bit
内存宽度：	9	功能数量：	1
端子数量：	32	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	64KX9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	3.556 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.43 mm
Base Number Matches：	1

CY7C4281-10JIT 数据手册

CY7C4281

CY7C4291

64K/128K x 9 Deep Sync FIFOs

Features

Functional Description

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64K × 9 (CY7C4281)

• 128K × 9 (CY7C4291)

• 0.5-micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power

— I_CC= 40 mA

— I_SB= 2 mA

The CY7C4281/91 are high-speed, low-power FIFO

memories with clocked read and write interfaces. All are nine

bits wide. The CY7C4281/91 are pin-compatible to the

CY7C42X1 Synchronous FIFO family. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor inter-

faces, and communications buffering.

These FIFOs have nine-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and two

write-enable pins (WEN1, WEN2/LD).

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and programmable Almost Empty and

Almost Full status flags

• TTL compatible

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• 32-pin PLCC

• Pin-compatible density upgrade to CY7C42X1

family

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1, WEN2/LD is held active, data is continually written into

the FIFO on each WCLK cycle. The output port is controlled in

a similar manner by a free-running read clock (RCLK) and two

read enable pins (REN1, REN2). In addition, the

CY7C4281/91 has an output enable pin (OE). The read

(RCLK) and write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 100 MHz are achievable. Depth expansion

is possible using one enable input for system control, while the

other enable is controlled by expansion logic to direct the flow

of data.

• Pin-compatible density upgrade to

IDT72201/11/21/31/41/51

0 −

Pin Configuration

Logic Block Diagram

INPUT

PLCC

Top View

WCLK WEN1 WEN2/LD

32 31 30

PAF

PAE

FLAG

PROGRAM

WEN1

WCLK

WEN2/LD

WRITE

CONTROL

CY7C4281

CY7C4291

GND

REN1

RCLK

REN2

PAE

PAF

FLAG

LOGIC

Dual Port

14 15 16 17 18 19 20

RAMARRAY

64K x 9

128K x 9

WRITE

POINTER

READ

POINTER

RESET

LOGIC

THREE-STATE

OUTPUT REGISTER

READ

CONTROL

0 –

RCLK REN1 REN2

Cypress Semiconductor Corporation

Document #: 38-06007 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 19, 2003

12 3 4 5 6 7...16

中文翻译

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与CY7C4281-10JIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C4281-15JC	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-25JC	CYPRESS	获取价格	64K/128K x 9 Deep Sync FIFOs
CY7C4281-25JCR	CYPRESS	获取价格	暂无描述
CY7C4281-25JI	CYPRESS	获取价格	FIFO, 64KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4281V	CYPRESS	获取价格	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
CY7C4281V-10JC	CYPRESS	获取价格	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
CY7C4281V-10JXC	CYPRESS	获取价格	16K/32K/64K/128K x 9 Low-Voltage Deep Sync⑩ F
CY7C4281V-15JC	CYPRESS	获取价格	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
CY7C4281V-15JCR	CYPRESS	获取价格	FIFO, 64KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4281V-15JCT	CYPRESS	获取价格	FIFO, 64KX9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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