Datasheet > CY7C2570XV18-633BZXC

CY7C2570XV18-633BZXC

更新时间： 2024-09-17 14:52:55

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
29页	902K
描述
DDR-II+ CIO

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C2570XV18-633BZXC 数据手册

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第2页

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第3页

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第4页

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第5页

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第6页

浏览型号CY7C2570XV18-633BZXC的Datasheet PDF文件第7页

CY7C2568XV18/CY7C2570XV18

72-Mbit DDR II+ Xtreme SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency) with ODT

72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ 72-Mbit density (4 M × 18, 2 M × 36)

With Read Cycle Latency of 2.5 cycles:

CY7C2568XV18 – 4 M × 18

■ 633 MHz clock for high bandwidth

CY7C2570XV18 – 2 M × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

1266 MHz) at 633 MHz

Functional Description

The CY7C2568XV18, and CY7C2570XV18 are 1.8 V

Synchronous Pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C2568XV18), or 36-bit words (CY7C2570XV18) that burst

sequentially into or out of the device.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo Clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for DQ_[x:0], BWS_[x:0], and K/K inputs

These devices have an On-Die Termination feature supported

for DQ_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

■ Synchronous internally self-timed writes

■ DDR II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Operates similar to DDR I Device with 1 cycle read latency

when DOFF is asserted LOW

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in Pb-free packages

For a complete list of related documentation, click here.

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

633 MHz

633

600 MHz Unit

600

910

MHz

Maximum Operating Current

× 18

× 36

965

1230

1165

Cypress Semiconductor Corporation

Document Number: 001-70206 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 19, 2014

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C2570XV18-633BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C2576KV18	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-400BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-400BZI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-400BZXC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-400BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-450BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-450BZI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-450BZXC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-450BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2576KV18-500BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

与CY7C2570XV18-633BZXC相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

10
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

8
SL74HC10N：高性能三输入与非门解析
2024-09-03

90
AIC1781A 电池充电控制器深度解析
2024-09-03

80

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C2570XV18-633BZXC

CY7C2570XV18-633BZXC 数据手册

与CY7C2570XV18-633BZXC相关器件

与CY7C2570XV18-633BZXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C2570XV18-633BZXC

CY7C2570XV18-633BZXC 数据手册

与CY7C2570XV18-633BZXC相关器件

与CY7C2570XV18-633BZXC相关文章

您还可以找

您在本页遇到什么问题？