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CY7C199L-25VCT

更新时间： 2024-11-21 13:01:03
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赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
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CY7C199L-25VCT 数据手册

 浏览型号CY7C199L-25VCT的Datasheet PDF文件第2页浏览型号CY7C199L-25VCT的Datasheet PDF文件第3页浏览型号CY7C199L-25VCT的Datasheet PDF文件第4页浏览型号CY7C199L-25VCT的Datasheet PDF文件第5页浏览型号CY7C199L-25VCT的Datasheet PDF文件第6页浏览型号CY7C199L-25VCT的Datasheet PDF文件第7页 
99  
CY7C199  
32K x 8 Static RAM  
provided by an active LOW Chip Enable (CE) and active LOW  
Output Enable (OE) and three-state drivers. This device has  
an automatic power-down feature, reducing the power con-  
sumption by 81% when deselected. The CY7C199 is in the  
standard 300-mil-wide DIP, SOJ, and LCC packages.  
Features  
• High speed  
— 10 ns  
• Fast tDOE  
An active LOW Write Enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE inputs  
are both LOW, data on the eight data input/output pins (I/O0  
through I/O7) is written into the memory location addressed by  
the address present on the address pins (A0 through A14).  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins are present on the eight data input/output pins.  
• CMOS for optimum speed/power  
• Low active power  
— 467 mW (max, 12 ns “L” version)  
• Low standby power  
— 0.275 mW (max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Functional Description  
The CY7C199 is a high-performance CMOS static RAM orga-  
nized as 32,768 words by 8 bits. Easy memory expansion is  
Logic Block Diagram  
Pin Configurations  
DIP / SOJ / SOIC  
Top View  
LCC  
Top View  
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
A
A
A
WE  
A
4
6
7
8
3
2 1 2827  
26  
4
A
4
A
A
10  
8
9
A
3
25  
24  
5
6
7
8
25  
24  
23  
22  
21  
20  
19  
18  
A
3
A
9
A
2
A
1
A
A
2
A
10  
A
11  
23  
22  
A
11  
A
1
A
12  
OE  
7
OE  
A
9
13  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
I/O  
I/O  
I/O  
A
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
0
0
1
2
3
4
5
6
8
9
10  
11  
12  
13  
0
A
10  
11  
12  
14  
INPUT BUFFER  
CE  
I/O  
I/O  
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617  
A
1
C199–3  
A
2
I/O  
I/O  
A
3
GND  
14  
3
A
4
C199–2  
1024 x 32 x 8  
ARRAY  
A
5
22  
OE  
A
A
21  
A
0
6
23  
24  
1
A
20  
CE  
I/O  
I/O  
6
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
1
7
A
A
A
A
2
3
4
19  
18  
17  
16  
8
A
7
25  
26  
27  
28  
1
9
5
TSOP I  
Top View  
(not to scale)  
WE  
4
3
CE  
WE  
V
CC  
A
15  
14  
13  
POWER  
DOWN  
COLUMN  
DECODER  
5
A
A
A
2
3
6
7
2
I/O  
7
12  
11  
OE  
4
5
8
9
I/O  
0
C199–1  
A
A
10  
9
14  
A
6
7
10  
A
A
13  
12  
A
11  
8
C199–4  
Selection Guide  
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45  
Maximum Access Time (ns)  
Maximum Operating  
8
10  
110  
90  
12  
160  
90  
15  
155  
90  
20  
150  
90  
25  
150  
80  
35  
140  
70  
45  
120  
140  
Current (mA)  
L
Maximum CMOS  
Standby Current (mA)  
0.5  
0.5  
0.05  
10  
10  
10  
10  
10  
10  
L
0.05  
0.05  
0.05  
0.05  
0.05  
Shaded area contains advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05160 Rev. **  
Revised September 7, 2001  
1234567...16

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