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CY7C199N-20ZXC PDF预览

CY7C199N-20ZXC

更新时间： 2024-11-21 02:53:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 487K
描述
32K x 8 Static RAM

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中文翻译

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CY7C199N-20ZXC 数据手册

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CY7C199N  
32K x 8 Static RAM  
Features  
Functional Description  
• High speed  
The CY7C199N is a high-performance CMOS static RAM  
organized as 32,768 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE) and active  
LOW Output Enable (OE) and three-state drivers. This device  
has an automatic power-down feature, reducing the power  
consumption by 81% when deselected. The CY7C199NN is in  
the standard 300-mil-wide DIP, SOJ, and LCC packages.  
— 12 ns  
• Fast tDOE  
• CMOS for optimum speed/power  
• Low active power  
— 467 mW (max, 12 ns “L” version)  
• Low standby power  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— 0.275 mW (max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Logic Block Diagram  
Pin Configurations  
DIP  
Top View  
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
A
A
A
WE  
A
4
6
7
8
A
3
25  
24  
A
9
A
2
A
1
A
10  
A
11  
23  
22  
7
OE  
A
A
A
I/O  
I/O  
I/O  
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
8
9
10  
11  
12  
13  
0
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUT BUFFER  
7
0
1
2
6
5
4
A
0
I/O  
I/O  
A
1
GND  
14  
A
3
2
A
3
22  
23  
OE  
A
A
21  
20  
A
0
4
1024 x 32 x 8  
ARRAY  
1
A
5
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
24  
A
2
3
4
6
19  
18  
17  
16  
7
6
25  
26  
27  
28  
1
A
7
A
8
5
4
3
TSOP I  
Top View  
(not to scale)  
A
WE  
9
V
CC  
15  
14  
13  
A
A
A
A
A
5
6
7
GND  
CE  
WE  
2
3
I/O  
2
POWER  
DOWN  
COLUMN  
DECODER  
12  
11  
I/O  
I/O  
A
1
0
14  
4
5
8
9
I/O  
7
10  
9
OE  
A
6
7
10  
A
A
13  
12  
A
11  
8
Selection Guide  
-12  
12  
-15  
-20  
-25  
25  
-35  
35  
-55  
55  
Unit  
ns  
Maximum Access Time  
15  
155  
90  
20  
150  
90  
Maximum Operating Current  
160  
90  
150  
80  
140  
70  
140  
70  
mA  
L
L
Maximum CMOS Standby Current  
10  
10  
10  
10  
10  
10  
mA  
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
Cypress Semiconductor Corporation  
Document #: 001-06493 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 2, 2006  
[+] Feedback  
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