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CY7C199-15ZCT

更新时间： 2024-11-29 13:01:55
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赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
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CY7C199-15ZCT 数据手册

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CY7C199  
32K x 8 Static RAM  
Functional Description  
Features  
• High speed  
The CY7C199 is a high-performance CMOS static RAM  
organized as 32,768 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE) and active  
LOW Output Enable (OE) and tri-state drivers. This device has  
an automatic power-down feature, reducing the power  
consumption by 81% when deselected. The CY7C199 is in the  
standard 300-mil-wide DIP, SOJ, and LCC packages.  
— 12 ns  
• Fast tDOE  
• CMOS for optimum speed/power  
• Low active power  
— 495 mW (Max, “L” version)  
• Low standby power  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— 0.275 mW (Max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Available in pb-free 28-pin TSOP I and 28-pin (300-Mil)  
Molded DIP  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Pin Configurations  
Logic Block Diagram  
DIP  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
A
4
6
A
A
7
8
A
3
25  
24  
A
9
A
2
A
10  
A
11  
23  
22  
A
1
7
OE  
A
A
A
I/O  
I/O  
I/O  
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
8
9
10  
11  
12  
13  
0
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CE  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUT BUFFER  
7
0
1
2
6
5
4
A
0
A
I/O  
I/O  
1
A
GND  
14  
2
3
A
3
A
4
22  
23  
OE  
A
32K x 8  
ARRAY  
21  
20  
A
0
A
5
1
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
A
6
A
A
A
24  
2
3
4
19  
18  
17  
16  
7
6
A
7
25  
26  
27  
28  
1
A
8
5
4
3
A
9
TSOP I  
Top View  
(not to scale)  
WE  
V
CC  
15  
14  
13  
A
A
A
A
A
5
6
7
GND  
I/O  
CE  
WE  
2
3
POWER  
DOWN  
2
COLUMN  
DECODER  
I/O  
1
12  
11  
4
5
8
9
I/O  
A
0
14  
I/O  
7
OE  
10  
9
A
6
10  
A
A
13  
12  
A
7
11  
8
Selection Guide  
–12  
12  
–15  
15  
–20  
20  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
160  
155  
90  
10  
150  
mA  
L
L
Maximum CMOS Standby Current  
10  
10  
mA  
0.05  
Cypress Semiconductor Corporation  
Document #: 38-05160 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
1234567...11

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