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CY7C199-20LMB PDF预览

CY7C199-20LMB

更新时间: 2024-11-28 22:39:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 319K
描述
32K x 8 Static RAM

CY7C199-20LMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:LCC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.11最长访问时间:20 ns
其他特性:AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:R-CQCC-N28JESD-609代码:e0
长度:13.97 mm内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8输出特性:3-STATE
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC28,.35X.55
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:1.905 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.17 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8.89 mm
Base Number Matches:1

CY7C199-20LMB 数据手册

 浏览型号CY7C199-20LMB的Datasheet PDF文件第2页浏览型号CY7C199-20LMB的Datasheet PDF文件第3页浏览型号CY7C199-20LMB的Datasheet PDF文件第4页浏览型号CY7C199-20LMB的Datasheet PDF文件第5页浏览型号CY7C199-20LMB的Datasheet PDF文件第6页浏览型号CY7C199-20LMB的Datasheet PDF文件第7页 
CY7C199  
32K x 8 Static RAM  
is provided by an active LOW Chip Enable (CE) and active  
LOW Output Enable (OE) and three-state drivers. This device  
has an automatic power-down feature, reducing the power  
consumption by 81% when deselected. The CY7C199 is in the  
standard 300-mil-wide DIP, SOJ, and LCC packages.  
Features  
• High speed  
— 10 ns  
• Fast tDOE  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
• CMOS for optimum speed/power  
• Low active power  
— 467 mW (max, 12 ns “L” version)  
• Low standby power  
— 0.275 mW (max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Functional Description  
The CY7C199 is a high-performance CMOS static RAM  
organized as 32,768 words by 8 bits. Easy memory expansion  
Logic Block Diagram  
Pin Configurations  
DIP / SOJ / SOIC  
LCC  
Top View  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
6
3
2 1 2827  
26  
A
A
A
4
7
4
A
4
A
8
8
A
3
25  
24  
5
6
7
8
25  
24  
23  
22  
21  
20  
19  
18  
A
A
9
3
A
9
A
2
A
1
A
A
10  
11  
12  
13  
14  
2
A
10  
A
11  
23  
22  
A
A
A
A
A
1
OE  
7
OE  
9
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
I/O  
I/O  
I/O  
A
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
0
0
1
2
3
4
5
6
8
9
10  
11  
12  
13  
0
10  
11  
12  
CE  
I/O  
I/O  
INPUT BUFFER  
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617  
A
1
A
2
I/O  
I/O  
A
GND  
3
14  
3
A
4
1024 x 32 x 8  
ARRAY  
22  
A
OE  
A
5
21  
A
0
A
23  
24  
1
6
A
20  
CE  
I/O  
I/O  
A
A
A
7
A
2
3
4
19  
18  
17  
16  
7
6
8
A
25  
26  
27  
28  
1
9
I/O  
I/O  
I/O  
GND  
I/O  
5
4
3
TSOP I  
Top View  
(not to scale)  
WE  
V
CC  
A
15  
14  
13  
CE  
WE  
5
6
7
POWER  
DOWN  
COLUMN  
DECODER  
A
A
A
2
3
2
12  
11  
I/O  
I/O  
A
1
0
14  
I/O  
4
5
7
8
9
OE  
A
10  
9
A
6
7
10  
A
A
13  
12  
A
11  
8
Selection Guide  
7C199 7C199  
7C199 7C199 7C199 7C199 7C199 7C199  
-8  
-10  
10  
-12  
12  
-15  
15  
-20  
20  
-25  
25  
-35  
35  
-45  
45  
Unit  
ns  
Maximum Access Time  
8
Maximum Operating Current  
120  
110  
90  
0.5  
0.05  
160  
90  
10  
155  
90  
10  
150  
90  
10  
150  
80  
10  
140  
70  
10  
140  
mA  
L
L
Maximum CMOS Standby Current  
0.5  
10  
mA  
0.05  
0.05  
0.05  
0.05  
0.05  
Shaded area contains advance information.  
Cypress Semiconductor Corporation  
Document #: 38-05160 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 7, 2003  

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