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CY7C185D

更新时间： 2024-11-14 04:53:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 182K
描述
64K (8K x 8) Static RAM

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CY7C185D 数据手册

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PRELIMINARY  
CY7C185D  
64K (8K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C185  
• High speed  
The CY7C185D is a high-performance CMOS static RAM  
organized as 8192 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE1), an active  
HIGH chip enable (CE2), and active LOW output enable (OE)  
and three-state drivers. This device has an automatic  
power-down feature (CE1 or CE2), reducing the power  
consumption when deselected.  
— tAA = 10 ns  
• Low active power  
— ICC = 60 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 3 mA  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE1 and WE  
inputs are both LOW and CE2 is HIGH, data on the eight data  
input/output pins (I/O0 through I/O7) is written into the memory  
location addressed by the address present on the address  
pins (A0 through A12). Reading the device is accomplished by  
selecting the device and enabling the outputs, CE1 and OE  
active LOW, CE2 active HIGH, while WE remains inactive or  
HIGH. Under these conditions, the contents of the location  
addressed by the information on address pins are present on  
the eight data input/output pins.  
• CMOS for optimum speed/power  
• Data Retention at 2.0V  
• Easy memory expansion with CE1, CE2, and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Available in Lead (Pb)-Free Packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.The CY7C185D is in a standard 28-pin  
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.  
Logic Block Diagram  
Pin Configurations  
DIP/SOJ/SOIC  
Top View  
NC  
V
CC  
1
2
3
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
WE  
CE  
4
A
5
2
I/O  
I/O  
0
A
A
3
6
4
5
INPUT BUFFER  
A
A
2
A
1
OE  
7
1
A
8
A
9
6
7
8
9
10  
11  
12  
13  
14  
A
A
0
10  
11  
12  
A
1
I/O  
I/O  
2
A
A
CE  
1
A
2
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
A
3
3
I/O  
0
I/O  
1
I/O  
2
A
256 x 32 x 8  
ARRAY  
4
A
5
I/O  
I/O  
I/O  
I/O  
4
5
6
7
A
GND  
6
A
7
A
8
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05466 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 10, 2005  
1234567...10

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