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CY7C185-20ZC PDF预览

CY7C185-20ZC

更新时间: 2024-11-19 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
12页 205K
描述
8K x 8 Static RAM

CY7C185-20ZC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP-28针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.8
最长访问时间:20 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:11.8 mm
内存密度:65536 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP28,.53,22封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.11 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.55 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

CY7C185-20ZC 数据手册

 浏览型号CY7C185-20ZC的Datasheet PDF文件第2页浏览型号CY7C185-20ZC的Datasheet PDF文件第3页浏览型号CY7C185-20ZC的Datasheet PDF文件第4页浏览型号CY7C185-20ZC的Datasheet PDF文件第5页浏览型号CY7C185-20ZC的Datasheet PDF文件第6页浏览型号CY7C185-20ZC的Datasheet PDF文件第7页 
185  
CY7C185  
8K x 8 Static RAM  
provided by an active LOW chip enable (CE1), an active HIGH  
chip enable (CE2), and active LOW output enable (OE) and  
three-state drivers. This device has an automatic power-down  
feature (CE1 or CE2), reducing the power consumption by 70%  
when deselected. The CY7C185 is in a standard 300-mil-wide  
DIP, SOJ, or SOIC package.  
Features  
• High speed  
— 15 ns  
• Fast tDOE  
• Low active power  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE1 and WE in-  
puts are both LOW and CE2 is HIGH, data on the eight data  
input/output pins (I/O0 through I/O7) is written into the memory  
location addressed by the address present on the address  
pins (A0 through A12). Reading the device is accomplished by  
selecting the device and enabling the outputs, CE1 and OE  
active LOW, CE2 active HIGH, while WE remains inactive or  
HIGH. Under these conditions, the contents of the location ad-  
dressed by the information on address pins are present on the  
eight data input/output pins.  
— 715 mW  
• Low standby power  
— 220 mW  
• CMOS for optimum speed/power  
• Easy memory expansion with CE1, CE2, and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
Functional Description[1]  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. A die coat is used to insure alpha immunity.  
The CY7C185 is a high-performance CMOS static RAM orga-  
nized as 8192 words by 8 bits. Easy memory expansion is  
Logic Block Diagram  
Pin Configurations  
DIP/SOJ/SOIC  
Top View  
NC  
V
CC  
1
2
3
4
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
WE  
CE  
4
A
5
2
A
A
3
6
A
A
2
A
1
7
5
I/O  
I/O  
0
A
8
6
7
8
9
10  
11  
12  
13  
14  
A
9
OE  
INPUT BUFFER  
A
A
A
A
0
10  
11  
12  
1
CE  
1
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
A
1
A
2
I/O  
0
I/O  
1
I/O  
2
I/O  
I/O  
2
A
3
3
GND  
A
256 x 32 x 8  
ARRAY  
4
A
5
I/O  
I/O  
I/O  
I/O  
4
5
6
7
A
6
A
7
A
8
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
Selection Guide[2]  
7C185-15  
15  
7C185-20  
20  
7C185-25  
25  
7C185-35  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
130  
110  
100  
100  
Maximum Standby Current (mA)  
40/15  
20/15  
20/15  
20/15  
Note:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
2. For military specifications, see the CY7C185A data sheet.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05043 Rev. *A  
Revised September 13, 2002  

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