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CY7C185-35VCT PDF预览

CY7C185-35VCT

更新时间: 2024-11-19 20:20:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 317K
描述
Standard SRAM, 8KX8, 35ns, CMOS, PDSO28, SOJ-28

CY7C185-35VCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.7最长访问时间:35 ns
其他特性:AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:R-PDSO-J28JESD-609代码:e0
长度:17.907 mm内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ28,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):220电源:5 V
认证状态:Not Qualified座面最大高度:3.556 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5057 mm
Base Number Matches:1

CY7C185-35VCT 数据手册

 浏览型号CY7C185-35VCT的Datasheet PDF文件第2页浏览型号CY7C185-35VCT的Datasheet PDF文件第3页浏览型号CY7C185-35VCT的Datasheet PDF文件第4页浏览型号CY7C185-35VCT的Datasheet PDF文件第5页浏览型号CY7C185-35VCT的Datasheet PDF文件第6页浏览型号CY7C185-35VCT的Datasheet PDF文件第7页 
fax id: 1013  
CY7C185  
8K x 8 Static RAM  
provided by an active LOW chip enable (CE ), an active HIGH  
Features  
1
chip enable (CE ), and active LOW output enable (OE) and  
2
• High speed  
— 15 ns  
three-state drivers. This device has an automatic power-down  
feature (CE or CE ), reducing the power consumption by 70%  
1
2
when deselected. The CY7C185 is in a standard 300-mil-wide  
DIP, SOJ, or SOIC package.  
• Fast t  
DOE  
• Low active power  
— 715 mW  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE in-  
1
• Low standby power  
— 220 mW  
puts are both LOW and CE is HIGH, data on the eight data  
2
input/output pins (I/O through I/O ) is written into the memory  
0
7
location addressed by the address present on the address  
pins (A through A ). Reading the device is accomplished by  
• CMOS for optimum speed/power  
• Easy memory expansion with CE , CE , and OE features  
• TTL-compatible inputs and outputs  
0
12  
1
2
selecting the device and enabling the outputs, CE and OE  
1
active LOW, CE active HIGH, while WE remains inactive or  
2
HIGH. Under these conditions, the contents of the location ad-  
dressed by the information on address pins are present on the  
eight data input/output pins.  
• Automatic power-down when deselected  
Functional Description  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. A die coat is used to insure alpha immunity.  
The CY7C185 is a high-performance CMOS static RAM orga-  
nized as 8192 words by 8 bits. Easy memory expansion is  
Logic Block Diagram  
Pin Configurations  
DIP/SOJ/SOIC  
Top View  
NC  
V
CC  
1
2
3
4
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
WE  
CE  
4
A
5
2
A
A
3
6
A
A
2
A
1
7
5
I/O  
I/O  
A
8
0
1
6
7
8
9
10  
11  
12  
13  
14  
A
9
OE  
INPUT BUFFER  
A
A
A
A
0
10  
11  
12  
CE  
1
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
A
1
A
2
I/O  
0
I/O  
1
I/O  
2
I/O  
I/O  
2
3
A
3
GND  
A
256 x 32 x 8  
ARRAY  
4
C185–2  
A
5
I/O  
I/O  
I/O  
I/O  
4
5
6
7
A
6
A
7
A
8
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
C185–1  
Selection Guide[1]  
7C185–15  
15  
7C185–20  
20  
7C185–25  
25  
7C185–35  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
130  
110  
100  
100  
40/15  
20/15  
20/15  
20/15  
Note:  
1. For military specifications, see the CY7C185A datasheet.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
August 12, 1998  

CY7C185-35VCT 替代型号

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IDT7164S35YG8 IDT

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