CY7C1663KV18/CY7C1665KV18
Pin Definitions (continued)
Pin Name
TDI
I/O
Input
Input
N/A
Pin Description
Test data-in (TDI) pin for JTAG.
TMS
Test mode select (TMS) pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
NC/288M
VREF
N/A
Not connected to the die. Can be tied to any voltage level.
Input-
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
Reference measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
valid 0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
Functional Overview
The CY7C1663KV18, CY7C1665KV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ completely eliminates the need to “turnaround” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of four 18-bit
data transfers in the case of CY7C1663KV18, and four 36-bit
data transfers in the case of CY7C1665KV18, in two clock
cycles.
When the read port is deselected, the CY7C1663KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
These devices operate with a read latency of two and half cycles
when DOFF pin is tied high. When DOFF pin is set low or
connected to VSS then device behaves in QDR I mode with a
read latency of one clock cycle.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1663KV18 is described in the following sections. The
same basic descriptions apply to CY7C1665KV18.
Read Operations
The CY7C1663KV18 is organized internally as four arrays of
2 M × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1663KV18. A
write operation is initiated as described in the section Write
Operations on page 6. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
Document Number: 001-44060 Rev. *M
Page 6 of 31
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
