Datasheet > CY7C1668KV18-450BZXC

CY7C1668KV18-450BZXC

更新时间： 2024-01-02 00:34:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
30页	771K
描述
144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1668KV18-450BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA,
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.77
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	150994944 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	15 mm	Base Number Matches：	1

CY7C1668KV18-450BZXC 数据手册

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CY7C1668KV18

CY7C1670KV18

144-Mbit DDR II+ SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency)

144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ 144-Mbit density (8 M × 18, 4 M × 36)

■ 550-MHz clock for high bandwidth

With Read Cycle Latency of 2.5 cycles:

CY7C1668KV18 – 8 M × 18

CY7C1670KV18 – 4 M × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

1100 MHz) at 550 MHz

Functional Description

The CY7C1668KV18, and CY7C1670KV18 are 1.8-V

synchronous pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C1668KV18), or 36-bit words (CY7C1670KV18) that burst

sequentially into or out of the device.

■ Available in 2.5-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ DDR II+ operates with 2.5-cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR I device with one cycle read latency

when DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

❐ Supports both 1.5-V and 1.8-V I/O supply

■ High-speed transceiver logic (HSTL) inputs and variable drive

HSTL output buffers

For a complete list of related documentation, click here.

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

■ Offered in Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

550 MHz

550

450 MHz Unit

450

790

980

MHz

Maximum operating current

× 18

× 36

910

1140

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-44062 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 1, 2017

12 3 4 5 6 7...30

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与CY7C1668KV18-450BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1668KV18-550BZXC	CYPRESS	获取价格	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1668KV18-550BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C166A-12DMB	ETC	获取价格	x4 SRAM
CY7C166A-12KMB	ETC	获取价格	x4 SRAM
CY7C166A-12LMB	ETC	获取价格	x4 SRAM
CY7C166A-15DC	ETC	获取价格	x4 SRAM
CY7C166A-15DMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 15ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
CY7C166A-15KMB	ETC	获取价格	x4 SRAM
CY7C166A-15LC	ETC	获取价格	x4 SRAM
CY7C166A-15LMB	ETC	获取价格	x4 SRAM

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