Datasheet > CY7C1623KV18-333BZXC

CY7C1623KV18-333BZXC

更新时间： 2024-02-16 16:11:29

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	773K
描述
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture

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CY7C1623KV18

144-Mbit DDR-II SIO SRAM Two-Word

Burst Architecture

144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture

Features

Configuration

■ 144-Mbit density (8 M × 18)

CY7C1623KV18 – 8 M × 18

■ 333 MHz clock for high bandwidth

Functional Description

The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM,

■ Two-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces (data transferred at

666 MHz) at 333 MHz

equipped with DDR-II SIO (Double Data Rate Separate I/O)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to ‘turnaround’ the data bus required with

common I/O devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 18-bit words that burst

sequentially into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self timed writes

■ DDR-II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR-I device with 1 cycle read latency

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V–V_DD

)

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA package (15 × 17 × 1.4 mm)

■ Offered in Pb-free package

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

333 MHz

333

250 MHz Unit

250

560

MHz

Maximum Operating Current

× 18

650

Cypress Semiconductor Corporation

Document Number: 001-44276 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 28, 2013

12 3 4 5 6 7...28

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与CY7C1623KV18-333BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C162-45DC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, CDIP28, DIP-28
CY7C162-45LC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, LCC-28
CY7C162-45PC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDIP28, DIP-28
CY7C162-45VC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDSO28, DSO-28
CY7C162-45VCR	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDSO28, PLASTIC, SOJ-28
CY7C1625KV18	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Two-Word Burst Archite
CY7C1625KV18-200BZC	CYPRESS	获取价格	QDR SRAM, 16MX9, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1625KV18-200BZXC	CYPRESS	获取价格	QDR SRAM, 16MX9, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1625KV18-250BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1625KV18-250BZXI	CYPRESS	获取价格	QDR SRAM, 16MX9, 0.45ns, CMOS, PBGA165, FBGA-165

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