Datasheet > CY7C1625KV18-250BZXI

CY7C1625KV18-250BZXI

更新时间： 2024-01-01 03:29:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
33页	626K
描述
QDR SRAM, 16MX9, 0.45ns, CMOS, PBGA165, FBGA-165

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技术参数
数据手册

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CY7C1625KV18-250BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	2.14
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	150994944 bit
内存集成电路类型：	QDR SRAM	内存宽度：	9
功能数量：	1	端子数量：	165
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	16MX9
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.37 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.78 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	15 mm	Base Number Matches：	1

CY7C1625KV18-250BZXI 数据手册

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CY7C1625KV18

CY7C1612KV18

CY7C1614KV18

144-Mbit QDR^®II SRAM Two-Word

Burst Architecture

144-Mbit QDR^®II SRAM Two-Word Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1625KV18 – 16 M × 9

CY7C1612KV18 – 8 M × 18

CY7C1614KV18 – 4 M × 36

■ 360-MHz clock for high bandwidth

■ Two-word burst on all accesses

Functional Description

■ Double data rate (DDR) interfaces on both read and write ports

The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18

are 1.8-V synchronous pipelined SRAMs, equipped with QDR II

architecture. QDR II architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to ‘turn around’ the

data bus that exists with common I/O devices. Access to each

port is through a common address bus. Addresses for read and

write addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 9-bit

words (CY7C1625KV18), 18-bit words (CY7C1612KV18), or

36-bit words (CY7C1614KV18) that burst sequentially into or out

of the device. Because data can be transferred into and out of

the device on every rising edge of both input clocks (K and K and

C and C), memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

(data transferred at 720 MHz) at 360 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR^®) II operates with 1.5-cycle read latency

when DOFF is asserted high

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted low

■ Available in × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Core V_DD= 1.8 V (± 0.1 V); I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

■ Available in 165-ball fine-pitch ball grid array (FBGA) package

(15 ×17 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

For a complete list of related documentation, click here.

■ Variable drive high-speed transceiver logic (HSTL) output

buffers

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

360 MHz

360

333 MHz

333

300 MHz

300

250 MHz Unit

250

780

800

950

MHz

Maximum operating current

× 9 Not Offered

950

880

× 18

1025

970

910

× 36 Not Offered

1160

1080

Cypress Semiconductor Corporation

Document Number: 001-16238 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 4, 2016

12 3 4 5 6 7...33

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与CY7C1625KV18-250BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1625KV18-300BZI	CYPRESS	获取价格	QDR SRAM, 16MX9, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1625KV18-333BZC	CYPRESS	获取价格	QDR SRAM, 16MX9, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1625KV18-333BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C162A-12DMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 12ns, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C162A-12KMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 12ns, CMOS, CDFP28, CERPACK-28
CY7C162A-12LMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 12ns, CMOS, CQCC28, CERAMIC, LCC-28
CY7C162A-15DC	ETC	获取价格	x4 SRAM
CY7C162A-15KMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 15ns, CMOS, CDFP28, CERPACK-28
CY7C162A-15LC	ETC	获取价格	x4 SRAM
CY7C162A-15PC	CYPRESS	获取价格	Standard SRAM, 16KX4, 15ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

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